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28529-dsh-001-k mindspeed technologies ? september 2007 mindspeed proprietary and confidential m28525/9 data sheet inverse multiplexing for atm (ima) family distinguishing features ? complete ima solution in a single package 16 port, m28525 32 port, m28529 field tested software available up to 32 ima groups with 1-32 links/group supports 50 ms (beyond the ima sta ndard requirements for 25 ms) differential delay with 512k internal memory memory expandable to 2 m bytes via external bus utopia level 2 interfaces glueless serial and interleaved highway interfaces to mindspeed framers octet or bit level cell delineation variable link data rates (64k?8.192 mb/s) the m2852x family of devices provides system designers with a complete integr ated ima solution for up to 32 ports. all devices include a transmission convergence block to perform cell delineation, 512 k internal ram to meet atm forum requirements for differential delay compensation and a dual mode (utopia or serial) phy layer interface. source code for all required software functions is available from mindspeed. the m28529 supports 32 ima groups with 1-32 links per group. the tc block is capable of bit level cell delineation, which allows for direct connection dsl serial data streams without a frame sync pulse. individual ports can be operated in a 'pass thru' mode without the ima overhead. the m28529 provides direct connection to 32 serial/interleaved highway links or a phy side utopia bus. in addition, an external memory bus allows the differential delay memory to access up to 2 mbytes of external ram.the m28529 supports both version 1.0 and 1.1 of ima standard af-phy-0086.001 functional block diagram p h y l a y e r u t o p i a 2 i n t e r f a c e im a engine line interface 0 c o n t r o l r e g i s t e r s im a c lo c ks t c status registers t c c ontrol registers micro interf ac e tc counters t x f i f o r x f i f o a t m l a y e r u t o p i a 2 i n t e r f a c e t x f i f o r x f i f o micro clocks m i c r o c l k 8 k h z i n o n e s e c i o s t a t u s r e g i s t e r s jtag a t m l a y e r u t o p i a i n t e r f a c e p i n s p h y s i d e i n t e r f a c e p i n s internal 512kx8 sr am external mem ory in te rfa c e extmemsel pin differential delay m em ory interface i p h y i n t f c s e l p i n s e r i a l / i n t e r l e a v e d m o d e e n a b l e d u t o p i a m o d e e n a b l e d t c b l o c k u t o p i a i n t e r f a c e i m a b y p a s s e n a b l e d i m a a n d t c e n a b l e d i m a b y p a s s e n a b l e d l o w h i g h i m a a n d t c e n a b l e d 1 0 c l o c k i n t e r f a c e onesec rx b lock and passthrough tx block and passthrough im a block tc b lock m 28529 i m a _ s y s c l k t x t r l [ 0 ] t x t r l [ 1 ] cell processor line interface 1 cell processor line interface 30 cell processor line interface 31 cell processor ... i m a _ r e f c l k *n ote: the m28525 only supports 16 tc ports
28529-dsh-001-k mindspeed technologies ? ii mindspeed proprietary and confidential ordering information model number manufacturing part number product revision package operating temperature m28525 m28525-12 b 27mm pbga, 484 pins ?40 c to 85 c m28525g* m28525g-12 b 27mm pbga, 484 pins ?40 c to 85 c m28529 m28529-12 b 27mm pbga, 484 pins ?40 c to 85 c m28529g* m28529g-12 b 27mm pbga, 484 pins ?40 c to 85 c *the g in the part number indicates that this is an rohs comp liant package. refer to www.mindsp eed.com for additional informati on. revision history revision level date description a advance april 2003 advance a version b advance may 2003 advance b version c advance july 2003 advance c version d advance august 2003 advance d version e advance october 2003 advance e version f preliminary february 2004 preliminary f version g preliminary may 2004 preliminary g version h released july 2004 released h version i released september 2004 released i version. added note to ima_fe_tx_lnkn_grp_id, ima_fe_tx_lnkn_cfg and atm cell capture registers to indicate conditions under which these registers will be undefined. j released august 2006 changes made to explain limitations in dual-clav mode, like, only addresses 0 through 0xf are supported and that multiple m28529 devices cannot share the utopia bus with an atm-layer device. k released september 2007 clarified configuration of pass-through operation. corrected minumum parameter for ?disable from atmutxclk rise edge.? other misc. corrections.
28529-dsh-001-k mindspeed technologies ? iii mindspeed proprietary and confidential table of contents ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi 1.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.1.1 introduction to ima . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.1.2 introduction to inverse multiplexing for atm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.1.2.1 ima framing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 1.1.2.2 ima control protocol cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1.2.3 link state machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.1.2.4 transmit clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.1.2.5 differential delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.1.3 software overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.1.3.1 software subsystems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1.1.3.2 configuration (cf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1.1.3.3 diagnostics (dg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1.1.3.4 failure monitoring (fm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1.1.3.5 performance monitoring (pm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1.1.3.6 group state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 1.2.1 ima features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 1.2.2 diagnostics/loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.2.3 cell delineation section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.2.4 control and status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.2.4.1 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.2.4.2 atm interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.2.4.3 phy interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.2.4.4 counters/status register section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.4 applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 1.4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
table of contents 28529-dsh-001-k mindspeed technologies ? iv mindspeed proprietary and confidential 1.4.2 dslam. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.4.3 wireless nodeb/rnc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.5 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.5.1 pin diagram and definitions (utopia-to-serial configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.5.2 pin diagram and definitions (utopia-to-utopia configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 1.5.3 interleaved highway configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 1.6 stand alone cell delineation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 1.7 source loopbacks (utopia-to-ser ial configuration only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 1.7.1 source loopback mode 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 1.7.2 source loopback mode 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 1.8 far-end line loopback (serial c onfiguration only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 1.9 ima line loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 1.10 ima system loopbacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 1.10.1 ima system loopback 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 1.10.2 ima system loopback 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 1.11 reference designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 1.12 ima clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 1.12.1 ima link rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 1.12.2 clock input requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 1.12.2.1 aggregate cell bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 1.12.2.2 serial clock sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 1.12.2.3 clock generator reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 1.12.3 summary examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 1.12.4 typical clock configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 1.12.4.1 serial mode (using internal tc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 1.12.4.2 utopia mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 1.12.5 ima internal timing examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 1.12.5.1 t1/e1 using internal serial ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 1.12.5.2 dsl/t1/e1 using utopia-to-utopia interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 1.13 utopia interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 1.13.1 general utopia operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 1.13.2 utopia 8-bit and 16-bit bus widths (phy and atm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 1.13.3 utopia interface blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 1.13.3.1 ima utopia . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 1.13.3.2 tc block utopia . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 1.13.3.3 phy-side utopia. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 1.13.4 dual clav/enb operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 1.14 transmission convergence block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 1.14.1 atm cell transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 1.14.1.1 hec generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 1.14.2 atm cell receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 1.14.2.1 cell delineation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 1.14.2.2 cell delineation control modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 1.14.2.3 cell screening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 1.14.2.4 cell scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
table of contents 28529-dsh-001-k mindspeed technologies ? v mindspeed proprietary and confidential 1.14.2.5 framing modes (utopia-to-serial configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 1.15 general issues. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 1.15.1 micro interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 1.15.1.1 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 1.15.1.2 counters (tc block only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 2.0 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 2.1 address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 2.2 tc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 2.2.1 0x00?sumint (summary interrupt indi cation status register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 2.2.2 0x01?ensumint (summary interrupt control register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 2.2.3 0x04?pmode (port mode control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 2.2.4 0x05?iomode (input/output mode control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 53 2.2.5 0x08?cgen (cell generation control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 2.2.6 0x09?hdrfield (header field control register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 2.2.7 0x0a?idlpay (transmit idle cell payload control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 5 2.2.8 0x0b?errpat (error pattern control re gister). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 2.2.9 0x0c?cval (cell validation control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 2.2.10 0x0d?utop1 (utopia control register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 2.2.11 0x0e?utop2 (utopia control register 2) (tc block). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 2.2.12 0x0f?udf2 (udf2 control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 2.2.13 0x10?txhdr1 (transmit cell header control register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 58 2.2.14 0x11?txhdr2 (transmit cell header control register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 59 2.2.15 0x12?txhdr3 (transmit cell header control register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 59 2.2.16 0x13?txhdr4 (transmit cell header control register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 60 2.2.17 0x14?txidl1 (transmit idle cell header control register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 60 2.2.18 0x15?txidl2 (transmit idle cell header control register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 61 2.2.19 0x16?txidl3 (transmit idle cell header control register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 61 2.2.20 0x17?txidl4 (transmit idle cell header control register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 62 2.2.21 0x18?rxhdr1 (receive cell header contro l register 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 2.2.22 0x19?rxhdr2 (receive cell header contro l register 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 2.2.23 0x1a?rxhdr3 (receive cell header control register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 63 2.2.24 0x1b?rxhdr4 (receive cell header control register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 64 2.2.25 0x1c?rxmsk1 (receive cell mask control register 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 2.2.26 0x1d?rxmsk2 (receive cell mask control re gister 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 2.2.27 0x1e?rxmsk3 (receive cell mask control register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 2.2.28 0x1f?rxmsk4 (receive cell mask control register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 2.2.29 0x20?rxidl1 (receive idle cell header c ontrol register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 2.2.30 0x21?rxidl2 (receive idle cell header c ontrol register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 2.2.31 0x22?rxidl3 (receive idle cell header c ontrol register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 2.2.32 0x23?rxidl4 (receive idle cell header c ontrol register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 2.2.33 0x24?idlms k1 (receive idle cell mask control register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 8 2.2.34 0x25?idlms k2 (receive idle cell mask control register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 9 2.2.35 0x26?idlms k3 (receive idle cell mask control register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 9 2.2.36 0x27?idlms k4 (receive idle cell mask control register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 0 2.2.37 0x28?encellt (transmit cell interrupt control register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 2.2.38 0x29?encellr (receive cell interrupt control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 2.2.39 0x2c?txcellint (transmit cell interrupt indication status register) . . . . . . . . . . . . . . . . . . . . . . . .171
table of contents 28529-dsh-001-k mindspeed technologies ? vi mindspeed proprietary and confidential 2.2.40 0x2d?rxcellint (receive cell interrupt indication status register) . . . . . . . . . . . . . . . . . . . . . . . . .172 2.2.41 0x2e?txcell (transmit cell status register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 2.2.42 0x2f?rxcell (receive cell status regist er). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 2.2.43 0x30?idlcntl (idle cell receive counter [low byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 2.2.44 0x31?idlcnth (idle cell receive counter [high byte]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 2.2.45 0x33?locdcnt (locd event counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 2.2.46 0x34?txcntl (transmitted cell counter [low byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 2.2.47 0x35?txcnth (transmitted cell counter [high byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 2.2.48 0x37?corrcnt (corrected hec error c ounter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 2.2.49 0x38?rxcntl (received cell counter [low byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 2.2.50 0x39?rxcnth (received cell counter [high byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 2.2.51 0x3b?unccnt (uncorrected hec error c ounter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 2.2.52 0x3c?noncntl (non-matching cell counter [low byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 2.2.53 0x3d?noncnth (non-matching cell counter [high byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 2.3 general control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 2.3.1 0xf00?genctrl (general device control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 2.3.2 0xf01?partnum (part and version number register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 2.3.3 0xf02?phyintfc (phy-side in terface control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 80 2.3.4 0xf03?atmintfc (atm-side interface cont rol register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 0 2.3.5 0xf04?statout (output status control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 2.3.6 0xf05?sumport0 (summary port interrupt status regist er for tc ports 0-7) . . . . . . . . . . . . . . . . .181 2.3.7 0xf06?ensumport0 (summary port interrupt control re gister for tc ports 0-7) . . . . . . . . . . . . . .181 2.3.8 0xf07?sumport1 (summary port interrupt status regist er for tc ports 8-15) . . . . . . . . . . . . . . . .182 2.3.9 0xf08?ensumport1 (summary port interrupt control register for tc ports 8-15) . . . . . . . . . . . . .182 2.3.10 0xf09?sumport2 (summary port interrupt status regi ster for tc ports 16-23) . . . . . . . . . . . . . . .183 2.3.11 0xf0a?ensumport2 (summary port interrupt control register for tc ports 16-23) . . . . . . . . . . . .183 2.3.12 0xf0b?sumport3 (summary port interrupt status register for tc ports 24-31) . . . . . . . . . . . . . . .184 2.3.13 0xf0c?ensumport3 (summary port interrupt control register for tc ports 24-31) . . . . . . . . . . . .184 2.3.14 0xf0f?scratch (scratch pad register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 2.3.15 0xf10?tcctrl0 (tc control register fo r tc ports 0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 2.3.16 0xf11?tcctrl1 (tc control register fo r tc ports 4-7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 2.3.17 0xf12?tcctrl2 (tc control register fo r tc ports 8-11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 2.3.18 0xf13?tcctrl3 (tc control register fo r tc ports 12-15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 86 2.3.19 0xf14?tcctrl4 (tc control register fo r tc ports 16-19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 87 2.3.20 0xf15?tcctrl5 (tc control register fo r tc ports 20-23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 87 2.3.21 0xf16?tcctrl6 (tc control register fo r tc ports 24-27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 88 2.3.22 0xf17?tcctrl7 (tc control register fo r tc ports 28-31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 88 2.3.23 0xf18?onesecint (one second interrupt status register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 2.3.24 0xf19?onesecint (one second interrupt control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 2.4 ima subsystem registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 2.4.1 0x800?ima_ver_1_config (ima type and version code i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 2.4.2 0x801?ima_ver_2_config (ima version codes ii and iii) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 2.4.3 0x802?ima_subsys_config (ima configur ation control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 2.4.4 0x803?ima_misc_status (ima miscellaneous status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 2.4.5 0x804?ima_misc_config (ima miscellaneous control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 2.4.6 0x805?ima_mem_low_test (i ma memory test address (bits 0?7)) . . . . . . . . . . . . . . . . . . . . . . .191 2.4.7 0x806?ima_mem_hi_test (ima memory test address (bits 8?15)) . . . . . . . . . . . . . . . . . . . . . . . .192 2.4.8 0x807?ima_mem_te st_ctl (ima memory test cont rol / address msbs) . . . . . . . . . . . . . . . . . . . .192 2.4.9 0x808?ima_mem_test_data (ima memory test data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
table of contents 28529-dsh-001-k mindspeed technologies ? vii mindspeed proprietary and confidential 2.4.10 0x809?ima_lnk_diag_ ctl (ima link diagnostic control register) . . . . . . . . . . . . . . . . . . . . . . . . .192 2.4.11 0x80a?ima_lnk_diff_del (i ma link differential delay write counter) . . . . . . . . . . . . . . . . . . . . . .192 2.4.12 0x80b?ima_rcv _lnk_anomalies (ima receive link anomalies). . . . . . . . . . . . . . . . . . . . . . . . . .193 2.4.13 0x80c?ima _phy_loopback (i ma phy side utopia loopback) . . . . . . . . . . . . . . . . . . . . . . . . . . .194 2.4.14 0x80e?ima_diag_xor_bit (ima diagnostic bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 2.4.15 0x80f?ima_diag (ima diagnostic register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 2.4.16 0x810?ima _tim_ref_mux_ctl_a ddr (ima timing reference multip lexer control address). . . . .195 2.4.17 0x811?ima_t im_ref_mux_ctl_dat a (ima timing reference multiplexer control data) . . . . . . . .196 2.4.18 0x812?ima_rx_persist_co nfig (ima receive persisten ce configuration) . . . . . . . . . . . . . . . . . .197 2.4.19 0x813?ima_atm_utopia_bus_ ctl (ima atm utopia bus control) . . . . . . . . . . . . . . . . . . . . . . .197 2.4.20 0x814?ima_diff_ delay_addr (ima differential delay control address). . . . . . . . . . . . . . . . . . . . .198 2.4.21 0x815?ima_diff_delay_ data (ima differential delay control data) . . . . . . . . . . . . . . . . . . . . . . . .198 2.4.22 0x816?ima_dsl_clock_gen_addr (ima dsl clock generator control) . . . . . . . . . . . . . . . . . . . .199 2.4.23 0x817?ima_dsl_clock_gen_data (ima _dsl clock generator data) . . . . . . . . . . . . . . . . . . . . . .200 2.4.24 0x818?ima_rx_trans_table (ima r eceive translation table address) . . . . . . . . . . . . . . . . . . . . .201 2.4.25 0x819?ima_rx_atm_tran s_table (ima receive atm tr anslation table internal channel). . . . . .202 2.4.26 0x81b?ima_ tx_trans_table (ima transmit tr anslation table address) . . . . . . . . . . . . . . . . . . . .203 2.4.27 0x81c?ima_tx_atm_tra ns_table (transmit atm translation table internal channel) . . . . . . . .203 2.5 ima group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 2.5.1 0x81f?ima_grp_1to4_sem (group table control i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 2.5.2 0x91f?ima_grp_5to8_sem (group table c ontrol ii) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 2.5.3 0xa1f?ima_grp_9to12_sem (group table control iii) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 2.5.4 0xb1f?ima_grp_13to16_sem (g roup table control iv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 2.5.5 0xc1f?ima_grp_17to20_sem (group table control v (m28529 only)) . . . . . . . . . . . . . . . . . . . . .206 2.5.6 0xc9f?ima_grp_21to24_sem (group table control v (m28529 only)) . . . . . . . . . . . . . . . . . . . . .207 2.5.7 0xd1f?ima_grp_25to28_sem (group tabl e control v (m28529 only)) . . . . . . . . . . . . . . . . . . . . .207 2.5.8 0xd9f?ima_grp_29to32_sem (group tabl e control v (m28529 only)) . . . . . . . . . . . . . . . . . . . . .208 2.5.9 ima_tx_grpn_rx_test_pattern (transmit group rx test pattern) . . . . . . . . . . . . . . . . . . . . . . . .208 2.5.10 ima_tx_grpn_ctl (transmit group control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 2.5.11 ima_tx_grpn_ first_phy_addr (transmit first phy address) . . . . . . . . . . . . . . . . . . . . . . . . . . . .210 2.5.12 ima_tx_grpn_id (transmit group id). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 2.5.13 ima_tx_grpn_stat_ctl (tra nsmit group status and control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212 2.5.14 ima_tx_grpn_timing_info (t ransmit timing information) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 2.5.15 ima_tx_grpn_test_c tl (transmit test control). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 2.5.16 ima_tx_grpn_tx _test_pattern (transmit group tx test pattern) . . . . . . . . . . . . . . . . . . . . . . . .215 2.5.17 ima_tx_atmn_c ell_count_lsb (transmit cell count lsbs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 2.5.18 ima_tx_atmn_c ell_count_msb (transmit ce ll count msbs) . . . . . . . . . . . . . . . . . . . . . . . . . . . .217 2.5.19 ima_rx_atm n_cell_count_lsb (receive cell count ls bs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 2.5.20 ima_rx_atmn_cell_count_msb (receive cell count msbs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 2.5.21 ima_rx_grpn_cfg (receive grou p status and control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 0 2.5.22 ima_rx_grpn_c tl (receive group control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 2.5.23 ima_rx_grpn_first_phy_addr (receive first phy address) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 2.5.24 ima_rx_grpn_id (e xpected receive group id). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 2.5.25 ima_rx_grpn_rx _test_pattern (receive group rx test pattern). . . . . . . . . . . . . . . . . . . . . . . . .224 2.5.26 ima_rx_grpn_stat_c tl_change (receive group status & control change indication) . . . . . . . . .225 2.5.27 ima_rx_grpn_act ual_grp_id (actual receive group id). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 2.5.28 ima_rx_grpn_sta t_ctl (receive group status and control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 2.5.29 ima_rx_grpn_timi ng_info (receive timing information) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228 2.5.30 ima_rx_grpn_test_c tl (receive test control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
table of contents 28529-dsh-001-k mindspeed technologies ? viii mindspeed proprietary and confidential 2.5.31 ima_rx_grpn_tx_t est_pattern (receive group tx test pattern) . . . . . . . . . . . . . . . . . . . . . . . . .230 2.6 ima link registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 2.6.1 0x81e?ima_lnk_sem (link table control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 30 2.6.2 ima_tx_lnkn_ctl (transmit link control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 2.6.3 ima_tx_lnkn_state (tra nsmit link status register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 2.6.4 ima_tx_lnkn_id (transmit link id register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 2.6.5 ima_rx_lnkn _ctl (receive link control register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 2.6.6 ima_rx_lnkn_s tate (receive link status register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 2.6.7 ima_rx_lnkn_defect (receive li nk defects register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 7 2.6.8 ima_fe_tx_lnkn_cfg (fe transmit configuration register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 2.6.9 ima_fe_lnkn_state (fe link status register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 2.6.10 ima_rx_l nkn_id (receive link id register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 2.6.11 ima_rx_lnkn_iv_cnt (ima violation c ounter register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 41 2.6.12 ima_rx_lnkn_oif_cnt (out-of-ima frame counter register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 2.6.13 ima_fe_tx_lnkn_grp_id (fe transmit group id register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 2.7 atm cell capture registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 2.7.1 0xe00-0xe2f?cell_cap_payldn (capture payload contents register) . . . . . . . . . . . . . . . . . . . . . .244 2.7.2 0xe30?cap_fac (capture facility register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 2.7.3 0xe31?cap_cntl (capture control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 2.7.4 0xe32?cap_stat (capture status register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 3.0 product specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246 3.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 3.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 3.4 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 3.4.1 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 3.4.2 microprocessor timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 3.4.3 phy-side interface timing (serial mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 3.4.4 fractional t1/e1 mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 3.4.5 phy-side interface mode (interleaved hi ghway) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 3.4.6 phy-side interface timing (utopia) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 3.4.7 utopia interface timing (atm-side). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264 3.4.8 external memory interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 3.4.9 jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268 3.4.10 one-second interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 3.5 package specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270 3.5.1 mechanical description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270 3.6 interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272 4.0 appendices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 4.1 ima version 1.1 pics proforma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 4.1.1 scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 4.1.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 4.1.3 symbols and conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 4.1.4 conformance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 4.1.5 ima pics proforma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276 4.1.5.1 global statement of conformance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 76
table of contents 28529-dsh-001-k mindspeed technologies ? ix mindspeed proprietary and confidential 4.1.5.2 instructions for completing the pics proforma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276 4.1.5.3 ima protocol functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276 4.1.6 pics proforma references. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 4.2 boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 4.3 power sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
28529-dsh-001-k mindspeed technologies ? ix mindspeed proprietary and confidential list of figures figure 1-1. m28525/9 block diagram example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 1-2. ima overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 figure 1-3. ima frame; length = 16; number of links = 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 figure 1-4. m2852x connected to a cx28398 transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 1-5. m28529 in dslam applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 1-6. m28529 in nodeb/rnc application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 1-7. m28529 logic diagram (utopia-to-serial) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 1-8. m28529 utopia-to-serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 1-9. m28529 logic diagram (utopia-to-utopia) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 1-10. ima block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 1-11. non-ima application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 figure 1-12. source loopback diagram (for simp licity the diagram shows the tc block only.) . . . . . . . . . . . . . . . . . . . . . . . .66 figure 1-13. far-end line loopback (this only shows the tc bl ock.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 figure 1-14. ima line loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 1-15. ima system loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 figure 1-16. m28529 clock diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 figure 1-17. typical t1/e1 configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 figure 1-18. serial dsl configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 figure 1-19. t1/e1 configurations (utopia mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 figure 1-20. dsl configurations (utopia mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 figure 1-21. t1/e1 using internal serial port s; ima_sysclk equals 24x line rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 figure 1-22. t1/e1 using internal serial ports; ima_refclk equals line rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 figure 1-23. dsl?utopia-to-utopia . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 figure 1-24. atm layer utopia interface connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 figure 1-25. m28529 multiple utopia control lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 figure 1-26. details of the tc block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 figure 1-27. cell delineation process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 figure 1-28. header error check process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 figure 1-29. cn8370 interface diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 figure 1-30. cn8370 interface - t1 timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 figure 1-31. cn8370 interface - e1 timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 figure 1-32. fractional t1 timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
list of figures 28529-dsh-001-k mindspeed technologies ? x mindspeed proprietary and confidential figure 1-33. fractional e1 timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 figure 1-34. dsl mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 figure 1-35. general purpose mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 figure 1-36. interfacing interleaved highway to cx2839x (frame sync provided by cx2389x) . . . . . . . . . . . . . . . . . . . . . . .101 figure 1-37. interfacing interleaved highway to cx2839x (frame sync externally provided) . . . . . . . . . . . . . . . . . . . . . . . . .102 figure 1-38. combined datastreams on the inte rleaved highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 figure 1-39. full t1 interleaved highway frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 figure 1-40. full e1 interleaved highway frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 figure 1-41. interleaved highway mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 figure 1-42. interrupt indication flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 figure 1-43. interrupt indication diagram (tc block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 figure 3-1. input waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 figure 3-2. output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 figure 3-3. reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 figure 3-4. microprocessor timing ?asynchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 figure 3-5. microprocessor timing ?asynchronous write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251 figure 3-6. microprocessor timing ?synchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 figure 3-7. microprocessor timing ?synchronous write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253 figure 3-8. phy-side serial t1/e1/dsl mode transmit timing (txclk pol = 0, txdatshft = 0) . . . . . . . . . . . . . . . . . . . . . . .254 figure 3-9. phy-side serial t1/e1/dsl mode transmit timing (txclk pol = 1, txdatshft = 0) . . . . . . . . . . . . . . . . . . . . . . .254 figure 3-10. phy-side serial t1/e1/dsl mode transmit timing (txclk pol = 0, txdatshft = 1) . . . . . . . . . . . . . . . . . . . . . . .255 figure 3-11. phy-side serial t1/e1/dsl mode transmit timing (txclk pol = 1, txdatshft = 1) . . . . . . . . . . . . . . . . . . . . . . .255 figure 3-12. phy-side serial t1/e1/ dsl mode receive timing (positive clock edge timing - rxclkpol = 0) . . . . . . . . . . . . . 256 figure 3-13. phy-side serial t1/e1/ dsl mode receive timing (negative clock edge timi ng- rxclkpol = 1) . . . . . . . . . . . . .2 56 figure 3-14. fractional t1/e1 transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 figure 3-15. fractional t1/e1 receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 figure 3-16. phy-side interl eaved highway mode transmit timing (ihtxclkpolx = 0, ihtxdatshftx = 0)) . . . . . . . . . . . . . . .259 figure 3-17. phy-side interleaved highway mode transmit timing (ihtxclkpolx = 1, ihtxdatshftx = 0) . . . . . . . . . . . . . . .259 figure 3-18. phy-side interleaved highway mode transmit timing (ihtxclkpolx = 0, ihtxdatshftx = 1) . . . . . . . . . . . . . . .260 figure 3-19. phy-side interleaved highway mode transmit timing (ihtxclkpolx = 1, ihtxdatshftx = 1) . . . . . . . . . . . . . . .260 figure 3-20. phy-side interleaved highway mode receive timing (positive edge - ihrxclkpolx = 0) . . . . . . . . . . . . . . . . . .261 figure 3-21. phy-side interleaved hi ghway mode receive timing (negative edge - ihrx clkpolx = 1) . . . . . . . . . . . . . . . . . .261 figure 3-22. phy-side utopia transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 figure 3-23. phy-side utopia receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 figure 3-24. atm-side utopia transm it timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264 figure 3-25. atm-side utopia receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265 figure 3-26. external memory timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 figure 3-27. jtag timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268 figure 3-28. one-second timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 figure 3-29. m28525/9 mechanical drawing (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
list of figures 28529-dsh-001-k mindspeed technologies ? xi mindspeed proprietary and confidential figure 3-30. m28525/9 mechanical drawing (top and side views) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 figure 3-31. m28529 pinout diagram, utopia-to-serial (bottom view ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272 figure 3-32. m28525 pinout diagram utopia-to-serial (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273 figure 3-33. m28525/9 pinout diagram utopia-to-utopia (bottom view ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274
28529-dsh-001-k mindspeed technologies ? xi mindspeed proprietary and confidential list of tables table 1-1. ima overhead cell definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 table 1-2. ima overhead filler cell format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 1-3. link states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 1-4. memory requirements for differential delay (in bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 1-5. software function summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 1-6. group state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 1-7. available parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 1-8. m28529 utopia-to-serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 1-9. m28529 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 1-10. utopia-to-utopia configuration information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 1-11. m2852x pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 1-12. serial stream muxing into interleaved highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 table 1-13. m28529 interleaved highway pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 table 1-14. interleaved highway port 0 - 3 pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 table 1-15. interleaved highway port 4 - 7 pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table 1-16. no connects per interleaved highway group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table 1-17. cell delineation configuration information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 table 1-18. reference clock configurations / sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 table 1-19. ima block clock sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 table 1-20. link rate resolution for variable rate applications (direct serial clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 table 1-21. link rate resolution for variable rate applications (internal bit rate generator) . . . . . . . . . . . . . . . . . . . . . . . . . .73 table 1-22. maximum aggregate bandwidth examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 table 1-23. ima serial clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 table 1-24. ima reference clock summary examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 table 1-25. device configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 table 1-26. control bit functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 table 1-27. cell screening?matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 table 1-28. cell screening?accept/reject cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 table 2-1. address ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 table 2-2. device control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 table 2-3. port control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 table 2-4. cell transmit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
list of tables 28529-dsh-001-k mindspeed technologies ? xii mindspeed proprietary and confidential table 2-5. cell receive registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 table 2-6. utopia registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 table 2-7. status and interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 table 2-8. status and interrupt registers (o ffset registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 table 2-9. counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 table 2-10. ima control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 table 3-1. absolute maximum ratings (general) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246 table 3-2. absolute maximum ratings (m28525/m28529) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246 table 3-3. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 table 3-4. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 table 3-5. power characteristics (m28529) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 table 3-6. reset timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 table 3-7. microprocessor timing parameters - asynchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251 table 3-8. microprocessor timing parameters - asynchronous write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 table 3-9. microprocessor timing parameters - synchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253 table 3-10. microprocessor timing parameters - synchronous write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 table 3-11. phy-side serial t1/e1/dsl mode transmit timing parame ters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255 table 3-12. phy-side serial t1/e1/ dsl mode receive timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256 table 3-13. fractional t1/e1 transmit timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 table 3-14. fractional t1/e1 receive timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 table 3-15. phy-side interleaved high way mode transmit timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260 table 3-16. phy-side interleaved hi ghway mode receive timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 table 3-17. phy-side utopia transmit timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 table 3-18. phy-side utopia receive timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 table 3-19. atm-side utopia transmit timing parameters (ima ena bled - 16 bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . .264 table 3-20. atm-side utopia tran smit timing parameters (ima bypassed - 8/16 bit mode, ima enabled - 8 bit mode) 265 table 3-21. atm-side utopia receive timing parameters (ima enabled - 16 bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . .266 table 3-22. atm-side utopia r eceive timing parameters (ima by passed - 8/16 bit mode, ima enabled - 8 bit mode) 266 table 3-23. external memory timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268 table 3-24. jtag timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 table 3-25. one second timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 table 4-1. basic ima protocol (bip) definition functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276 table 4-2. qos requirements functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280 table 4-3. ctc and itc operation functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280 table 4-4. ima data cell (idc) rate implementation functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 table 4-5. link differential delay (ldd) functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 table 4-6. ima interface operation (iio) functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 table 4-7. ima frame synchronization (ifs) mechanism functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285
list of tables 28529-dsh-001-k mindspeed technologies ? xiii mindspeed proprietary and confidential table 4-8. ima interface oam operat ion functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 table 4-9. test pattern procedure (tpp) functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291 table 4-10. ima interaction with plane management functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 table 4-11. management information base (mib ) functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
28529-dsh-001-k mindspeed technologies ? 1 mindspeed proprietary and confidential 1.0 functional description 1.1 overview 1.1.1 introduction to ima this chapter provides a basic introduct ion to ima. it will introd uce common terminology, the ima frame format and ima cell structure. it will also address one of the challeng es of ima: differential dela y between links. for detailed coverage of these topics the reader should refer to the atm forum's standard for ima. the m2852x is composed of the following major functional blocks as shown in figure 1-1 . 1.1.2 introduction to inve rse multiplexing for atm bandwidth, or the lack thereof, has always been the main challenge of telecommunications. while numerous standards for high speed connections have been around for years, the cost of these higher speed connections often prohibit users from deploying them. for example, users who need a data rate higher than the standard t1, (1.544 mbps) must pay for an entire ds3 (44 mbps). often the extra cost cannot be justified. figure 1-1. m28525/9 block diagram example p h y l a y e r u t o p i a 2 i n t e r f a c e im a engine line interface 0 c o n t r o l r e g i s t e r s im a c loc ks t c status registers tc control registers micro interf ac e tc c ounters t x f i f o r x f i f o a t m l a y e r u t o p i a 2 i n t e r f a c e t x f i f o r x f i f o micro clocks m i c r o c l k 8 k h z i n o n e s e c i o s t a t u s r e g i s t e r s jtag a t m l a y e r u t o p i a i n t e r f a c e p i n s p h y s i d e i n t e r f a c e p i n s internal 512kx8 sr am e xte rn a l m e m o ry in te rfa c e extmemsel pin d if f e r e n t ia l d e la y memory interface i p h y i n t f c s e l p i n s e r i a l / i n t e r l e a v e d m o d e e n a b l e d u t o p i a m o d e e n a b l e d t c b l o c k u t o p i a i n t e r f a c e i m a b y p a s s e n a b l e d i m a a n d t c e n a b l e d i m a b y p a s s e n a b l e d l o w h i g h i m a a n d t c e n a b l e d 1 0 c l o c k i n t e r f a c e onesec rx block and passthrough t x b lock and passthrough im a block tc b loc k m 28529 i m a _ s y s c l k t x t r l [ 0 ] t x t r l [ 1 ] cell processor line interface 1 cell processor line interface 30 cell processor line interface 31 cell processor ... i m a _ r e f c l k *n ote: the m28525 only supports 16 tc ports
functional description 28529-dsh-001-k mindspeed technologies ? 2 mindspeed proprietary and confidential ima solves this problem by allowing us ers to purchase bandwidth in smaller increments and combine these smaller 'pipes' into one high speed connection. an example is given in figure 1-2 where 3 t1 lines are combined into one 4.6 mbps data link. at first glance, the concept of ima is deceptively simple: spread the atm cells out evenly over the available individual lines. however, many serious technical issues must be dealt with and a wide range of functions must be supported. these include ima framing, differential delay accommodation, link/group state machines, ima clocking, and maintenance. several terms must be defined: 1.1.2.1 ima framing the ima protocol employs a simple frame structure as shown in figure 1-3 . it consists of a single ima overhead cell (icp) and m ? 1 atm layer cells, where m is the ima frame length. valid frame lengths are 32, 64, 128 (default), or 256. this example shows a group composed of three links and an ima frame length of 16. (an invalid frame length of 16 is used for brevity, the default frame length is 128.) ima engine the logic that performs the actual ima function. this sits between the atm layer and the individual links (see figure 1-2 ). an ima engine can control multiple independent groups. link refers to an individual physical connection such as a t1 or dsl line. each link has an individual utopia address or serial connection to the ima engine. group an ima group is composed of links. a group appears as a single utopia address to the atm layer. thus an ima-4 group would have 4 individual links. group state machine the operation of the ima group is governed by the group state machine (gsm), the group traffic state machine (gtsm), and the link addition and slow recovery (l asr) procedure. these three processes ensure reliable transmission and reception of at m layer cells across all links in the acti ve state. this includ es the negotiation of group parameters (i.e., symmetry and m values), the br inging up of the ima group, and the graceful addition/ recovery and deletion of links to and from the group. for th e m28529, this function is performed in the host software. the software itself is available from mindspeed. link state machine a link state machine (l sm) is defined for the transmit and receive directions of each ima link. the ima proto col is defined to allow symmetric or asymmet ric cell rate transfer over the ima virtual link. it allows for smooth introduction of each link in the group. it also allows graceful handling of error conditions and removal of a link. this function is performed internally by the m28529. figure 1-2. ima overview 3 - t1 1.544 mb/s 4.5 mb/s 4.5 mb/s 1 3 2 2 1 3 3 2 1 500027_053
functional description 28529-dsh-001-k mindspeed technologies ? 3 mindspeed proprietary and confidential since the atm layer data rate is often less than the bandwidth available across the links in the ima group, the ima engine generates ima filler cells when no atm layer cells are available. (the ima f iller cells perform the same basic function as idle cells in a non-ima atm system and are discarded by the ima receiver.) the ima frame rate is intentionally set slightly below the available payload bandwidth of the ima link. to allow for timing differences between the links in a group, the ima standard requires that the system insert an extra icp cell every 2049 cells. this cell is called the sicp cell and is inserted immediately after the normal icp cell for that link and results in the frame being m+1 cells long. information in the icp cell payload signals the insertion of these cells so that the receiver does not lose framing and can identify and discard these cells. for further details consult the ima standard. one link in each group is designated the timing reference link (trl). all timing issues for the group are relative to this link. figure 1-3. ima frame; length = 16; number of links = 3 500027_067 icp 3 atm 4 atm 10 f icp 3 atm 21 icp 3 0 151413121110987654321 f f f atm 3 atm 2 atm 1 f f f f ima control protocol cell ifsn = n atm payload; cell x in the sequence filler cell 1 ima frame m = 16 atm x icp n f link 0 link 1 link 2 atm 5 atm 6 atm 7 atm 9 atm 8 atm 0 atm 12 atm 11 atm 16 atm 19 atm 14 atm 15 atm 13 atm 17 atm 18 atm 20 atm 27 atm 24 atm 30 atm 25 atm 23 atm 22 atm 28 atm 26 atm 34 atm 32 atm 29 atm 33 atm 31 atm 0 atm 2 atm 1 atm 3 atm 5 atm 4 atm 34 atm 33 atm 32 atm 35 atm 36 this cell will be in the next frame ... incoming data from the atm layer (which doesn't know that the data is being split into frames) data output into an ima frame atm x this cell was in the previous frame f delay between the cells arrival at the ima device results in filler cells being inserted f always at least 1 icp cell per frame this link selected as the timing reference link, (trl), thus first icp starts at 0.
functional description 28529-dsh-001-k mindspeed technologies ? 4 mindspeed proprietary and confidential 1.1.2.2 ima control protocol cells the ima standard defines three types of ima cells: ima control prot ocol (icp) cells, filler cells, and atm layer cells. icp cells are the ima overhead cells that carry the ima control and status information between both ends of the link, assuring syn chronization and configuration. t he purpose of filler cells is rate decoupling; they are inserted into the ima stream if no atm layer cells are available. atm layer cells are the data ?payload? carried by the ima group. these are the standard atm cells being sent from the atm layer. ta bl e 1-1 describes the ima overhead cell definition, and ta b l e 1-2 lists format of the ima overhead stuff cell. note: standard atm 'idle' cells are never transmitted over an ima link. table 1-1. ima overhead cell definition (1 of 3) octet field description 1-5 atm cell header oam cell type: octet 1 = 0000 0000 octet 2 = 0000 0000 octet 3 = 0000 0000 octet 4 = 0000 1011 octet 5 = 0110 0100 (val id hec with coset) 6 ima label oam type field: 0000 0001?ima version 1.0 0000 0011?ima version 1.1 7cell id link id bit 7 set to 1 for icp cell bits 6?5 unused and set to 0 bits 4?0 logical id for physical link range (0... 31) 8 frame sequence number cyclical counter: 0 to 255 9 icp cell offset indicates position of i cp cell within the ima frame of size m cells. range: (0... m ? 1) 10 link stuff indication (lsi) stu ff indication code for link on which icp cell is being sent bits 7?3 unused and set to 0 bits 2?0 111: no imminent stuff (default) 100: stuff event in 4 icp cell locations (optional) 011: stuff event in 3 icp cell locations (optional) 010: stuff event in 2 icp cell locations (optional) 001: stuff event at the next icp cell location (mandatory) 000: this is one out of the 2 icp cell s comprising the stuff event (mandatory) 11 status / control change indication (scci) status and control change indication: 0 to 255 and cycling (count to be incremented every time there is a change to octets 12 to 49). 12 ima id logical ima group id
functional description 28529-dsh-001-k mindspeed technologies ? 5 mindspeed proprietary and confidential 13 group status & cont rol bits 7?4 group status 0000: start-up 0001: start-up-ack 0010: config-aborted: unsupported m 0011: config-aborted: incompatible symmetry 0100: config-aborted: unsupported ima version 01xx: available for other config abort reasons 1000: insufficient-links 1001: blocked 1010: operational bits 3?2 others: reserved symmetry of group 00: symmetrical confi guration and operation 01: symmetrical configurati on and asymmetric operation 10: asymmetrical conf iguration and operation bits 1?0 11: reserved ima frame length 00: m=32 01: m=64 10: m=128 11: m=256 14 transmit timing informatio n transmit clock information bits 7?6 unused, set to 00 bit 5 transmit clock mode (0: itc mode, 1: ctc mode) bits 4?0 tx lid of the timing re ference link (trl)?range: 0 to 31 15 tx test control test pattern command bits 7?6 unused, set to 00 bit 5 test link command (0: inactive, 1: active) bits 4?0 tx lid of te st link?range: 0 to 31 16 tx test pattern value from 0 to 255 17 rx test pattern value from 0 to 255 table 1-1. ima overhead cell definition (2 of 3) octet field description
functional description 28529-dsh-001-k mindspeed technologies ? 6 mindspeed proprietary and confidential 18 link 0 information link state machine and defect information for link with lid = 0 bits 7?5 transmit lsm state bits 4?2 receive lsm state bits 1?0 rx link defect status 00: no errors 01: physical link defect (e.g., los, oof/lof, lcd) 10: lif 11: lods 19?49 link 1?31 info status and control of link with lid in the range 1?31 50 unused set to 0x6a (as defined in itu-t i.432) 51 end-to-end channel proprietary channel (set to 0 if unused). the m2852x does not support this octet. 52?53 crc error control bits 15-10 reserved field for future use?default value is all zeros bits 9-0 crc-10 as defined in itu-t recommendation i.610 table 1-2. ima overhead filler cell format octet field description 1?5 atm cell header oam cell type: octet 1 = 0000 0000 octet 2 = 0000 0000 octet 3 = 0000 0000 octet 4 = 0000 1011 octet 5 = 0110 0100 (valid hec) 6 ima label oam type field: 0000 0001?ima version 1.0 0000 0011?ima version 1.1 7cell id link id bit 7 set to 0 for ima filler cell bits 6?0 unused and set to 0 8?51 unused set to 0x6a (as defined in itu-t i.432) 52?53 crc error control bits 15-10 reserved field for future use?default value is all zeros bits 9-0 crc-10 as defined in itu-t recommendation i.610 table 1-1. ima overhead cell definition (3 of 3) octet field description
functional description 28529-dsh-001-k mindspeed technologies ? 7 mindspeed proprietary and confidential 1.1.2.3 link state machine management of the individual links is performed by two state machines: the transmit link state machine and the receive link state machine. four possible states are available for each link as shown in ta bl e 1-3 . the link state machines are responsible for handling the transition from one state to another. all functions of the lsm's are performed internally by the m2852x. further details are covered in section 1.12 and in the atm standard on ima. 1.1.2.4 transmit clocks the ima standard provides two options regarding the transmit clocks. the default mode, and most common ima application, is common tran smit clock (ctc) mode, where all links in the ima group are generated from the same source. thus they are in phase and have the same rate of sicp insertion (1/2049) as the designated trl link. the independent transmit clock (itc) mode is available as an optional feature of the ima protocol (of course, it is fully supported by the m2852x family). in this mode, each link runs off of an independent clock at the nominal line rate. to support these asynchronous links within an ima group, the rate of sicp insertion is allowed to vary on the non-trl links. the ima group frame rate for each ima group must be re-created at the receive end. this regeneration is necessary to implement the ima data cell clock and smoothing buffer functionality of the ima protocol. one method for generating the receive ima group frame rate is to use the line or payload clock recovered from the receive trl physical port interface. this clock is a frequency locked reference of the far-end transmit ima group frame rate. equivalently, the rate of cell transfers (i.e., payload bandwidth) from the trl link can be used as the reference for generating the receive ima group frame rate. both methods are available for use by the m2852x device, depending on the application and configuration. 1.1.2.5 differential delay when dealing with multiple facilities, there is no guarant ee that the individual links wit hin a group will take the same physical path between the terminating equipment. this variation is referred to as differential delay. the atm forum specification requires an ima implementation to absorb a minimum of 25 ms of differential delay between the links. each link requires 8 k of memory for every 27.5 ms of delay (at e1; 8 k provides for 34.375 ms at t1 rates). the m28525/9 provides 512k bytes of on-board memory for the buffering necessary to re-align the links within an ima group. this is sufficient to support the 50 ms of delay (at e1 rates) for 32 ima ports. in addition, an external memory bus allows this to be expanded to 2 mb, which supports up to 200 ms of delay. ta b l e 1-4 shows the memory requirements for differential delay. table 1-3. link states state description not in group this link has not been added to an ima group unusable the link is in a group but cannot be used due to line fault etc. usable assigned to a group and ready but is waiting for the other end active fully configured and carrying traffic
functional description 28529-dsh-001-k mindspeed technologies ? 8 mindspeed proprietary and confidential the magnitude of the differential delay can be quite large when dealing with t1/e1 links; whereas dsl links generally follow the same path and have nearly identical delays. 1.1.3 software overview all ima devices require a software driver to interface to the system host. since the gsm's primary function only occurs during startup; the m2852x family relies on the ima driver to perform these functions. this allows for maximum flexibility; simpler devi ce design and requires very lit tle overhead from the host. mindspeed provides a complete ima and device driver in ansi c to simplify system development. this software has been field tested and can be ported to virtually all systems. this is also covered in chapter 3, the ima engine and the m28529tap ima software programming guide. ta bl e 1-5 summarizes the api of the m28525/9 software. all functions require a pointer to the structure ima_dev. the additional parameters for each function are listed in the following sections. the functions named ima_xxxx() are function calls to the m28525/9. the functions named user_xxxx() are user defined functions called by the m28525/9. the pointers to the user defined functions are passed to m28525/9 during initialization as fields in the drv initialization structure or after initialization using the ima_subsys_set() function. table 1-4. memory requirements for differential delay (in bytes) number of links e1 27.5 ms 55 ms 110 ms 220 ms t1 34.375 ms 68.75 ms 137.5 ms 275 ms 1 8 k 16 k 32 k 64 k 2 16 k 32 k 64 k 128 k 4 32 k 64 k 128 k 256 k 8 64 k 128 k 256 k 512 k 16 128 k 256 k 512 k 1024 k 32 256 k 512 k 1024 k 2048 k general note: shaded areas can be supported by internal memory. internal memory is disabled when the external bus is used. note: mindspeed?s software supports both tc and ima; however, this section only describes ima software support. table 1-5. software function summary (1 of 2) class function short description initialization ima_init_default () initializes the fields of the m28525/9 initialization structure to default values. ima_init () this function initializes the ima software driver and the ima device. interrupts ima_tick () this function polls the error counter s and failure monitoring registers of the ima device and must be called at a regular periodic interval. ima_intr () this function should be called when the device interrupt line has been asserted.
functional description 28529-dsh-001-k mindspeed technologies ? 9 mindspeed proprietary and confidential ima subsystem ima_read () this function pr ovides a direct interface to read th e registers within the ima device. ima_write () this function provides a direct interface to write the registers within the ima device. ima_subsys_set () this function provid es a direct interface to set the m28525/9 subsystem parameters. ima_subsys_get () this function provides a direct interface to retrieve the m28525/9 subsystem parameters. ima_test () this function executes a specified ima diagnostic test. ima_facility_set() this function prov ides a direct interface to set the m28525/9 facility parameters. ima_facility_get() this function provides a direct interface to retrieve the m28525/9 facility parameters. group interface ima_group_set () this function provides a direct interface to set the m28525/9 group parameters. ima_group_get () this function provides a direct interface to retrieve the m28525/9 group parameters. ima_group_fm_status () this function retrieves the current state of the parameters monitored by the facility monitoring subsystem for the ima group layer. ima_group_pm_preset () this function allows the user to init ialize the ima group pm statistics to arbitrary values for the current interval of the 15 minute accumulation period. ima_group_pm_status () this function retrieves the states (from either the current or previous 15 minute accumulation interval) of the ima group performance monitoring parameters. link interface ima_link_set () this f unction provides a direct interface to set the m28525/9 link parameters. ima_link_get () this function provides a direct interface to retrieve the m28525/9 link parameters. ima_link_fm_status () this f unction retrieves the current state of the parameters monitored by the facility monitoring subsystem for the ima link layer. ima_link_pm_preset () this function allows the user to init ialize the ima link pm stat istics to arbitrary values for the current interval of the 15 minute accumulation period. ima_link_pm_status () this function retrieves the states (from either the current or previous 15 minute accumulation interval) of the ima link performance monitoring parameters. phy interface ima_phy_link_set () this f unction provides a direct interface to set the m28525/9 link parameters, per facility. ima_phy_link_get () this function provides a direct interface to retrieve the m28525/9 link parameters, per facility. ima_phy_link_fm_status () this function retrieves the current state of the parameters monitored by the failure monitoring subsystem for the ima link layer, per facility. ima_phy_link_pm_preset () thi s function allows the user to initialize th e ima group pm statistics to arbitrary values for the current interval of the 15 minute accumulation period. ima_phy_link_pm_status () this function retrieves the states (from either th e current or previous 15 minute accumulation interval) of the ima link perfor mance monitoring parameters, per facility. monitor ima_mon() this function is called to control the m28525/9 debugger. user defined *user_intr_disable() this is an application defined function that disables interrupts from the ima hardware device. *user_intr_enable() this is an application defined fu nction that enables interrupts from the ima hardware device. * user_event () this is an application defined function that accepts asynchronous event messages from the m28525/9 software. table 1-5. software function summary (2 of 2) class function short description
functional description 28529-dsh-001-k mindspeed technologies ? 10 mindspeed proprietary and confidential 1.1.3.1 software subsystems the internal architecture of the m28529tap software is composed of five logical subsystems: configuration (cf), diagnostics (dg), ima group (grp), failure monitoring (fm), and performance monitoring (pm). the following sections summarize the interfaces of the m28525/9 ima software device driver. it is important to point out that the m28525/9 products can be configured to run in different operating environments. as such, not all the interfaces described below are used in a given application. 1.1.3.2 configuration (cf) the cf subsystem is responsible for setting the operating parameters of the ima device that are associated with the ima link and ima group termination entities. additionally , some of the application specific configurations of the device are set by this subsystem. the default value for each parameter is used to initialize and set the operating mode of the device. 1.1.3.3 diagnostics (dg) the dg subsystem performs control and testing functions on the ima device and its environment. one role of the dg subsystem is configuration, very similar to the cf subsystem but with different parameters. similar in function to the configuration subsystem, the default value for each dg parameter is used to initialize and set the operating mode of the device. the dg subsystem parameters are typically exercised only during test or maintenance conditions, and may affect atm transmission through the device. 1.1.3.4 failure monitoring (fm) the failure monitoring (fm) subroutine is responsible for monitoring the ima links and groups for defects and anomalies and integrating the defects into failures. the primary role performed by this subsystem is alarm integration. the m28529tap program is aware of changes in the state of the underlying defects and anomalies through periodic polling. the user has control over which failure indicators are monito red and the length of both the activation and decay times. upon initializing the m28529tap, the failure indications required by the atm mib are enabled and the activation and decay times are set at 2.5 and 10 seconds, respectively. 1.1.3.5 performance monitoring (pm) this is the set of function s and capabilities necessary for a network el ement (ne) to gather , store, and report performance data associated with its monitored digital transmission entities. in contrast with alarm/status indications, performance parameters are quantitative, not binary, in nature. these performance parameters are gathered over programmable, predetermined accumulation periods. the m28529tap calculates these statistics over 15 minute intervals. the pm data is available to the application grouped in a structure encompassing one of the two accumulation sets: the current 15 minute interval or the previous 15 minute interval. the pm subsystem uses the raw anomaly and defect information obtained by th e fm subsystem to calculate its performance statistics. upon initialization, the pm subsystem is basically disabled: none of the monitored statistics are calculated. 1.1.3.6 group state machine overall management of each group is th e responsibility of the group state machine. this actually involves three interrelated processes: the group state machine (gsm), the group traffic state machine (gtsm), and the link addition and slow recovery (lasr) procedure. these three processes are used to ensure reliable transmission and reception of atm layer cells across all links in the active state. this includes the negotiation of group parameters (i.e., symmetry and m values), the bringing up of the ima group, and the graceful addition/recovery and
functional description 28529-dsh-001-k mindspeed technologies ? 11 mindspeed proprietary and confidential deletion of links to and from the group. the seven possible states are shown in ta b l e 1-6 . again, this will be covered in more detail in chapter 1.12 and in the atm standard on ima. 1.2 features 1.2.1 ima features complete ima solution in a single package 16 port, m28525 32 port, m28529 field proven design all software available supports variable link data rates (64k?8.192 mb/s) supports fractional t1/e1 per af-phy-0130.00 512 k internal memory supports 50 ms (beyond the ima standard requirements for 25 ms) differential delay with 512k internal memory connects directly to the mindspeed sars for inexpensive cpe solutions m28525 supports 16 facilities up to 16 independent groups: each group can have up to 16 links. m28529 supports 32 facilities up to 32 independent groups: each group can have up to 32 links. memory expandable to 2 m bytes via external bus supports ima versions 1.0 and 1.1 table 1-6. group state machine state description not configured no groups configured start up waiting to establish communications with the other end start up ack start up acknowledge; has recognized the fa r end and waiting to enter the insufficient links state config aborted results when the far end doesn?t comply with the requested configuration parameters insufficient links both ends have accepted the group paramete rs and are waiting for the lsm to provide active links blocked the host controller has inhibited the group (probably for maintenance reasons) operational fully operation al and able to pass data
functional description 28529-dsh-001-k mindspeed technologies ? 12 mindspeed proprietary and confidential 1.2.2 diagnostics/loopbacks source loopback far end line loopback ima line loopback ima system loopback icp cell access ieee 1149.1 jtag interface 1.2.3 cell delineation section supports atm cell interface for: circuit-based physical layer cell-based physical layer performs single-bit hec correction and single- or multiple-bit detection inserts headers and generates hec direct connection to external mindspeed components for: t1/e1 xdsl general purpose mode byte-level or bit-level cell delineation 1.2.4 control and status 1.2.4.1 microprocessor interface asynchronous sram-like interface mode 8-bit data bus open-drain interrupt output open-drain ready output up to 66 mhz operation all control registers are read/write 1.2.4.2 atm interface atm-side utopia interface: 8/16-bit utopia level 2 slave up to 50 mhz operation support for dual clav and enable signals supports 32 atm addresses
functional description 28529-dsh-001-k mindspeed technologies ? 13 mindspeed proprietary and confidential 1.2.4.3 phy interfaces phy-side utopia interface: 8/16-bit utopia level 2 master supports 32 ports via dual clav and enable lines serial interface interleaved highway up to 33 mhz operation 1.2.4.4 counters/status register section summary interrupt indications configuration of interrupt enables one-second counter latching counters for: locd events corrected hec errors uncorrected hec errors transmitted cells matching received cells non-matching received cells idle cell receive 1.3 general description the m2852x family of devices provides system designers with a complete integrated ima solution for up to 32 ports. all devices include a transmission convergence block to perform cell delineation, 512 k internal ram to meet atm forum requirements for differential delay compensation and a dual mode (utopia or serial) phy layer interface. source code for all required software functions is available from mindspeed. the m28529 supports 32 ima groups with 1-32 links per group. the tc block is capable of bit level cell delineation, which allows for direct connection dsl serial data streams without a frame sync pulse. individual ports can be operated in a 'pass thru' mode without the ima overhead. the m28529 provides direct connection to 32 serial/interleaved highway links or a phy side utopia bus. in addition, an external memory bus allows the differential delay memory to access up to 2 mbytes of external ram.the m28529 supports both version 1.0 and 1.1 of ima standard af-phy-0086.001
functional description 28529-dsh-001-k mindspeed technologies ? 14 mindspeed proprietary and confidential 1.4 applications 1.4.1 overview the m2852x is typically used with line framer devices like the cx28398 t1/e1 octal framer or the m28985 zipwiremulti? octal g.shdsl transceiver wi th embedded microprocessor . figure 1-4 illustrates a typical application. figure 1-4. m2852x connected to a cx28398 transceiver atm switch or sar im a processor m28259 o ctal t1/e1 framer port 0 port 1 port 7 port 2 port 3 port 4 port 5 port 6 port 16 port 17 port 23 port 18 port 19 port 20 port 21 port 22 port 8 port 9 port 15 port 10 port 11 port 12 port 13 port 14 port 24 port 25 port 31 port 26 port 27 port 28 port 29 port 30 liu 1 liu 2 liu 3 liu 4 liu 5 liu 6 liu 7 liu 8 liu 8 liu 10 liu 11 liu 12 liu 13 liu 14 liu 15 liu 16 liu 17 liu 18 liu 19 liu 20 liu 21 liu 22 liu 23 liu 24 liu 25 liu 26 liu 27 liu 28 liu 29 liu 30 liu 31 liu 32 cx28398 cx28398 cx28398 cx28398 o ctal t1/e1 framer o ctal t1/e1 framer o ctal t1/e1 framer utopia level 2 bus microprocessor bus tx1 rx1 tx2 rx2 tx3 rx3 tx4 rx4 quad liu cx28380 tx5 rx5 tx6 rx6 tx7 rx7 tx8 rx8 quad liu cx28380 tx9 rx9 tx10 rx10 tx11 rx11 tx12 rx12 quad liu cx28380 tx13 rx13 tx14 rx14 tx15 rx15 tx16 rx16 quad liu cx28380 tx17 rx17 tx18 rx18 tx19 rx19 tx20 rx20 quad liu cx28380 tx21 rx21 tx22 rx22 tx23 rx23 tx24 rx24 quad liu cx28380 tx25 rx25 tx26 rx26 tx27 rx27 tx28 rx28 quad liu cx28380 tx29 rx29 tx30 rx30 tx31 rx31 tx32 rx32 quad liu cx28380
functional description 28529-dsh-001-k mindspeed technologies ? 15 mindspeed proprietary and confidential 1.4.2 dslam digital subscriber line access multiplexers (dslam) and broadband loop carriers (blc) are being deployed to provide broadband services to business and residential customers. although dsl and t1/e1 services delivers higher speeds than traditional dial-up connections, customers are increasingly finding the need for higher bandwidth than is available through a single dsl or t1/e1 line. the ima protocol helps bridge the gap between lower cost xdsl solutions and higher cost lines such as t3. ima allows customers to scale their bandwidth needs in t1/e1 or xdsl link increments, so they do not have to pay for more than they can use. figure 1-5 shows a typical example of how ima can be used to meet the evolving needs of customers. the dslam can use the m28529 32-port ima controller with the octal m28985 dsl modem chip for the customer access side. the cx28225 4-port ima can be used in the dsl cpe equipment to complete the solution for providing flexible bandwidth scaling. on the network side, dslams generally need to backhaul customer traffic to the atm backbone. this can be done by bonding multiple t1s to gether using ima. this lin e card is also shown in figure 1-4 . the m28529 can be used once again with mindspeed's cx28395 16-port framers and cx28380 quad lius. a similar line card is needed at the atm/multiservice switch. 1.4.3 wireless nodeb/rnc wireless base transceiver stations (bts) and nodeb eq uipment for 3g based networks have a need to send customer's compressed voice/data from the base station to the radio network controller (rnc). many times, high speed fiber links are not available where the equipment is deployed. by using ima to bond multiple t1 or e1 links together, the traffic can be backhauled effectively and efficiently. figure 1-6 illustrates the nodeb/rnc example. the nodeb can either use a cx28229 fo r 8-ports or the m28529 for 16 to 32-port applications. the cx28398 framer and cx28380 complete the line card. the rnc can aggregate traffic from multiple base sites, so the m28529 can be used here. again, the cx28395 16-port framer and cx8380 quad lius can be used to complete the line card solution. figure 1-5. m28529 in dslam applications co co cpe cpe splitter-less adsl modem (uadsl, g.lite) dslam dslam co/street cabinet co/street cabinet atm switch atm switch nxt1/e1 links m28529 ima controller m28529 ima controller atm layer device atm layer device framer cx28395 framer cx28395 serial serial utopia dslam uplink card or atm switch card liu cx28380 liu cx28380 liu cx28380 liu cx28380 m28529 ima controller m28529 ima controller atm layer device atm layer device liu cx28380 liu cx28380 cx28985 dsl cx28985 dsl utopia utopia liu cx28380 liu cx28380 liu cx28380 liu cx28380 m28529 ima controller m28529 ima controller atm layer device atm layer device liu cx28380 liu cx28380 cx28985 dsl cx28985 dsl utopia utopia dslam access line card liu cx28380 x8 liu cx28380 x8
functional description 28529-dsh-001-k mindspeed technologies ? 16 mindspeed proprietary and confidential 1.5 pin definitions two versions of mindspeed's ima solution are available: m28525 and the m28529. all use the same software drivers and are basically pin compatible. ta bl e 1-7 provides a quick comparison of the two devices. the following three configurations are available: utopia-to-serial * utopia-to-utopia utopia-to-interleaved highway* * note: interleaved highway can be mixed with serial mode on a per group of four channel basis. interleaved highway mode is enabled by setting the enihx (x = 0 to 7) bit in the appropriate tcctrlx (x = 0 to 7) register. figure 1-6. m28529 in nodeb/rnc application table 1-7. available parts device internal memory external memory interface utopia addresses (phy side) serial ports m28525 512 kbytes 2 mbyte (1) 0?15, 31 (null) 16 m28529 512 kbytes 2 mbyte (1) 0?31 (2) 32 footnote: (1) internal memory is disabled when the external bus is used. (2) normally, 0x1f is the null address; however, the m28529 can be configured to treat it as a valid port address. 8xt1/e1 links rf subsystem nodeb rnc atm layer device atm layer device framer cx28395 framer cx28395 liu cx28380 x8 liu cx28380 x8 32-port solution m28529 ima controller m28529 ima controller cx28229 ima controller cx28229 ima controller atm layer device atm layer device liu cx28380 liu cx28380 framer cx28398 framer cx28398 liu cx28380 x2 liu cx28380 x2 cx28229 ima controller cx28229 ima controller atm layer device atm layer device liu cx28380 liu cx28380 framer cx28398 framer cx28398 liu cx28380 x2 liu cx28380 x2 utopia serial serial utopia serial serial
functional description 28529-dsh-001-k mindspeed technologies ? 17 mindspeed proprietary and confidential 1.5.1 pin diagram and definitions (utopia-to-serial configuration) figure 1-7 illustrates a pinout diagram for the m28529 when op erating in utopia-to-serial mode. it is a single cmos integrated circuit packaged in a 484-pin pbga. all unused input pins should be connected to ground or power. unused outputs and bi-directional pins should be left unconnected. figure 1-8 is a block diagram of an 32 link ima solution using the device in the utopia-to-serial mode to take advantage of the internal serial ports. cell delineation is per formed internally and the m2852x interfaces directly to the framers. these framers could be t1/e1 or dsl. further details can be found in the mindspeed reference design available online. configur ation information is shown in ta b l e 1-8 . note: utopia-to-serial configur ation is selected by tyi ng the phyintfcsel pin high.
functional description 28529-dsh-001-k mindspeed technologies ? 18 mindspeed proprietary and confidential figure 1-7. m28529 logic diagram (utopia-to-serial) reset i reset* reset 8khzin clock i 8khzin* one second interface i/o one second input/output onesecio receive clock i receive data i receive data marker i i transmit clock i/o transmit data marker o transmit data sprxclk[0] sprxdata[0] sprxsync[0] sptxclk[0] sptxdata[0] sptxsync[0] sprxclk[31] sprxdat a[ 31] sprxsync[31] i transmit clock o transmit data sptxclk[31] sptxdata[31] sptxsync[31] i/o transmit data marker line interface port 0 line interface port 31 phy interface select i sync/async mode select i microprocessor clock i chip select i address strobe, write control i write/read read control i address bus i o status output o summary interrupt o ready i/o microprocessor data bus phyintfcsel (1) msyncmode mi cr ocl k mcs * mas*, mwr mw/ r, mrd * microaddr[11:0] microprocessor interface test reset i test clock i test mode select i test data input i test enable i test mode i trst * tck tms tdi testenable testmode tdo jtag interface atm utopia transmit interface statout [1:0] microint * mrdy microdata[7:0] atm transmit clock i atm transmit enable i atm transmit address bus i atmutxclk atmutxenb[1:0] * atmutxaddr[4:0] o test data output atmutxclav[1:0] atmutxsoc atmutxprty atmutxdata[15:0] o atm transmit cell available i atm transmit parity i atm transmit data bus atm utopia receive interface atmurxclk atmurxenb[1:0] * atmurxaddr[4:0] atm recei ve cl ock i atm receive enable i atm receive address bus i atmurxsoc atmurxprty atmurxdata[15: 0] o atm receive cell available o atm receive parity o atm recei ve dat a bus ima system clock i ima_sysclk ima_refclk ima reference clock i ima clocks txtrl[1:0] o transmit reference clock external memory interface memdata[15:0] memory data bus i/o extmemsel external memory select i memaddr[19:0] o memory address bus o chip enable memct r l _ce * o output enable memct r l _oe * o write enable memct r l _we * o sram clock memct r l _cl k memct r l _adsc* o address enable (1) pulled high i atm transmit start of cell o atm receive start of cell atmurxclav[1:0] recei ve dat a i receive data marker i recei ve cl ock i
functional description 28529-dsh-001-k mindspeed technologies ? 19 mindspeed proprietary and confidential figure 1-8. m28529 utopia-to-serial mode table 1-8. m28529 utopia-to-serial mode atmmux [7,6] (atmintfc, 0xf03) phyintfcsel (pin ad24) description 01 high ima utopia using internal tc block; utopia-to-serial mode using 32 internal serial ports. general note: external memory coul d be used if desired (m28525/9). phy layer utopia 2 interface ima engine line interface 0 line interface 1 line interface 30 line interface 31 cell processor cell processor cell processor cell processor control registers ima clocks ima_sysclk ima_refclk tc status registers tc control registers micro interface tc counters tx fifo rx fifo atm layer utopia 2 interface tx fifo rx fifo micro clocks microclk 8khzin onesecio status registers jtag internal 512kx8 sram extmemsel pin differential delay memory interface phyintfcsel pin tc block utopia interface low high ima and tc enabled 1 0 clock interface onesec rx block and passthrough tx block and passthrough ima block tc block m2852x 500027_069 extended memory txtrl[0] txtrl[1] ima bypass enabled
functional description 28529-dsh-001-k mindspeed technologies ? 20 mindspeed proprietary and confidential table 1-9. m28529 pin descriptions (1 of 19) pin label signal name no. i/o description micro interface statout[0] status output ab24 o general pur pose output pins under software control. statout[1] ad26 msyncmode microprocessor synchronous/ asynchronous bus mode select ae24 i/pd selects synchronous or asynchronous bus mode, which determines the functions of two pins, mw/r,mrd* (pin w4) and mas*,mwr* (pin y2). a logic 1 selects the synchronous bus mode. in this mode, these pins are defined as follows: mw/r (w4) and mas* (y2). a logic 0 selects the asynchronous sram-type bus mode. in this mode, the pins are defined as follows: mrd* (w4) and mwr* (y2). reset* device reset t4 i/pu when asserted low, r esets the device. the microprocessor clock must be present before reset is released. if configuring the device for pass-through operation, a minimum delay of 25 us for ima_sysclk of 66 mhz or 33us for ima_sysclk of 50 mhz is required from the release of reset to the first access of the ima_rx_trans_table register or the ima_rx_atm_trans_table register (0x818/0x819). 8khzin 8 khz input ad25 i a clock input used to derive onesecio. typically operates at a frequency of 8 khz. onesecio one-second input/output ae26 i/o software can confi gure this pin as an output that equals the input from the 8khzin divided by 8000. when configured as an input, status registers and counters may be latched on the rising edge of this input. see bit 0 of the genctrl register (0xf00). mw/r, mrd* microprocessor write/ read w4 i when msyncmode is asserted high, this pin is a read/write control pin. in this mode, when mw/r is asserted high, a write access is enabled and the microdata[7:0] pi n values will be written to the memory location indicated by the microaddr[11:0] pins. also, when mw/r is asserted low in this mode, a read access is enabled and the memory location indicated by the microaddr[11:0] pins is read. its value is placed on the micr odata[7:0] pins. both read and write accesses assume the device is chip selected (mcs* = 0), the address is valid (mas* = 0), and the device is not being reset (reset* = 1). when msyncmode is asserted low, this pin is a read control pin. in this mode, when mrd* is asserted low, a read access is enabled and the memory location indicated by the microaddr[11:0] pins is read. its value is placed on the microdata[7:0] pins. mcs* microprocessor chip select v1 i when asserted low, the device is selected for read and write accesses. when asserted high, the devi ce will not respond to input signal transitions on microclk, mw/r, mrd*, or mas*, mwr*. additionally, when mcs* is asserte d high, the microd ata[7:0] pins are in a high-impedance state but the microint* pin remains operational.
functional description 28529-dsh-001-k mindspeed technologies ? 21 mindspeed proprietary and confidential micro interface mas*, mwr* microprocessor address strobe y2 i when msyncmode is asserted high, this pin is an address strobe pin. when the mas* pin is asser ted low, it indicates a valid address, microaddr[11:0]. this signal is used to qualify read and write accesses. when msyncmode is asserted low, th is pin is a write control pin. when mwr* is asserted low, a write access is enabled and the microdata[7:0] pin valu es will be written to the memory location indicated by the microaddr[11: 0] pins. the write access assumes the device is chip selected (mcs* = 0), a read access is not being requested (mrd* = 1), and the devi ce is not being reset (reset* = 1). microaddr[0] microprocessor address bus u2 i these 12 bits are an address input for identifying the register to access. microaddr[1] t3 microaddr[2] u1 microaddr[3] t2 microaddr[4] r4 microaddr[5] t1 microaddr[6] r3 microaddr[7] r2 microaddr[8] p4 microaddr[9] r1 microaddr[10] p3 microaddr[11] p2 microdata[0] microprocessor data bus w3 i/o a bi-directional data bus for reading and writing data to internal registers. microdata[1] v4 microdata[2] y1 microdata[3] w2 microdata[4] v3 microdata[5] u4 microdata[6] w1 microdata[7] v2 microint* microprocessor interrupt request aa1 o when active low, the device need s servicing. it remains active until the pending interrupt is processed by the interrupt service routine. this pin is an open drain output for an or logic implementation. an external pull-up resistor is required for this pin. table 1-9. m28529 pin descriptions (2 of 19) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 22 mindspeed proprietary and confidential micro interface mrdy microprocessor ready y3 o when act ive high, the current read or write transaction has been completed. for a read transaction, the data is ready to be transferred to the microprocessor. for a write transaction, the data provided by the microprocessor has been written. this pin is an open drain output for an external wired or logic implementation. an external pull-up resistor is required for this pin. microclk microprocessor clock r5 i in asynchronous mode the microprocessor clock signal input can be clocked up to 66 mhz. in synchronous mode this pin can be clocked up to 25 mhz. the device samples the microprocessor interface pins (mcs*, mw/r, mas*, microaddr[11:0], and microdata[7:0]) on the rising edge of this signal. the microprocessor interface output pins (microdata[7:0], microint*) are clocked on the rising edge of mi croclk. note that this clock is required for both synchronous and asynchronous operations. see note in section 1.15.1 . external memory extmemsel external memory enable ac26 i/pd when this pin is pulled high, it enables the external differential delay sram bus. memdata[0] differential delay memory data bus m26 i/o/pd differential delay sram data bus. atm cells extracted from the receive data stream are stored in the sram for the purpose of differential delay compensation. this bus is enabled by pulling the extmemsel pin high. memdata[1] n24 memdata[2] n25 memdata[3] n26 memdata[4] p26 memdata[5] p25 memdata[6] p24 memdata[7] p23 memdata[8] r26 memdata[9] p22 memdata[10] r24 memdata[11] t26 memdata[12] r23 memdata[13] t25 memdata[14] t24 memdata[15] u26 table 1-9. m28529 pin descriptions (3 of 19) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 23 mindspeed proprietary and confidential external memory memaddr[0] differential delay memory address bus u25 o receive sram address bus this signal is enabled by pulling the extmemsel pin high. memaddr[1] t23 memaddr[2] v26 memaddr[3] u24 memaddr[4] v25 memaddr[5] w26 memaddr[6] u23 memaddr[7] v24 memaddr[8] w25 memaddr[9] y26 memaddr[10] v23 memaddr[11] w24 memaddr[12] y25 memaddr[13] aa26 memaddr[14] w23 memaddr[15] y24 memaddr[16] aa25 memaddr[17] y23 memaddr[18] ab26 memaddr[19] aa24 memctrl_ce* chip enable n23 o recei ve sram device select (act ive low) control signal. this signal is enabled by pulling the extmemsel pin high. memctrl_oe* output enable m25 o r eceive sram device output ( active low) control signal. this signal is enabled by pulling the extmemsel pin high. memctrl_we* write enable m24 o receive sram wr ite enable (active low) control signal. this signal is enabled by pulling the extmemsel pin high. external memory memctrl_clk sram clock ab25 o receive sram clock signal. this signal is enabled by pulling the extmemsel pin high. memctrl_adsc* address enable l26 o receive sram ad dress enable (active low) address strobe. this signal is enabled by pulling the extmemsel pin high. table 1-9. m28529 pin descriptions (4 of 19) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 24 mindspeed proprietary and confidential jtag trst* test reset c5 i/pu when asserted, the internal boundary-scan logic is reset. this pin has a pull-up resistor. tck test clock a2 i/pu samples the value of tms and tdi on its rising edge to control the boundary scan operations. tms test mode select d5 i/pu controls the boundary-scan test access port (tap) controller operation. this pin has a pull-up resistor. tdi test data input c4 i/pu the serial test da ta input. this pin has a pull-up resistor. tdo test data output c3 o the serial test data output. factory test testenable[0] af26 i/pd factory te st use only, tie to vss. testenable[1] ac22 scanenable ad23 i/pd factory test use only, tie to vss. tristate tristate ae25 i /pd when this pin is high, all outputs are tristate. phy side interface phyintfcsel phy interface select ad24 i/pu if this pin is tied low, the phy utopia interface mode is selected. if this pin is tied high, the phy serial mode is selected (as shown in this table). ima clocks ima_sysclk ima subsystem clock e18 i/pu most of the ima l ogic circuits use this clo ck (or a derivative of it). it can also be used as a t1/e1 reference clock. refer to section 1.12 . ima_refclk ima subsystem clock e16 i/pu if ref_xclk is to be used as a reference clock, set the frequency as shown in section 1.12 . txtrl[0] transmit reference clock a19 o transmit reference clocks. txtrl[1] b19 table 1-9. m28529 pin descriptions (5 of 19) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 25 mindspeed proprietary and confidential serial line interface sprxsync[0] frame sync input b17 i/pd when the phy serial interface is enabled, this is the frame sync input. note that ports 16-31 are no connects in the m28525. (1) sprxsync[1] a17 sprxsync[2] c16 sprxsync[3] b16 sprxsync[4] c11 sprxsync[5] b10 sprxsync[6] d11 sprxsync[7] a9 sprxsync[8] b4 sprxsync[9] d6 sprxsync[10] a3 sprxsync[11] d3 sprxsync[12] h1 sprxsync[13] k4 sprxsync[14] j3 sprxsync[15] j2 sprxsync[16] y4 sprxsync[17] aa3 sprxsync[18] ad1 sprxsync[19] ac2 sprxsync[20] ae6 sprxsync[21] ad7 sprxsync[22] ac8 sprxsync[23] af6 sprxsync[24] af12 sprxsync[25] ac13 sprxsync[26] ad13 sprxsync[27] ae13 sprxsync[28] ad18 sprxsync[29] ae19 sprxsync[30] af20 sprxsync[31] ad19 table 1-9. m28529 pin descriptions (6 of 19) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 26 mindspeed proprietary and confidential serial line interface sprxclk[0] receive line clock input b18 i/pd when the phy serial interface is enabled, this is the receive line clock input. note that ports 16?31 are no-connects in the m28525. (1) sprxclk[1] c17 sprxclk[2] a18 sprxclk[3] d16 sprxclk[4] a11 sprxclk[5] d12 sprxclk[6] b11 sprxclk[7] a10 sprxclk[8] b5 sprxclk[9] d7 sprxclk[10] c6 sprxclk[11] b3 sprxclk[12] g1 sprxclk[13] j4 sprxclk[14] h3 sprxclk[15] h2 sprxclk[16] aa2 sprxclk[17] ab1 sprxclk[18] ac1 sprxclk[19] ab2 sprxclk[20] ae5 sprxclk[21] ad6 sprxclk[22] ac7 sprxclk[23] af5 sprxclk[24] ac12 sprxclk[25] af11 sprxclk[26] ad12 sprxclk[27] ae12 sprxclk[28] ad17 sprxclk[29] ae18 sprxclk[30] af18 sprxclk[31] af19 table 1-9. m28529 pin descriptions (7 of 19) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 27 mindspeed proprietary and confidential serial line interface sprxdata[0] receive line data input d15 i/pd when the phy serial interface is enabled, this is the receive line data input. note that ports 16?31 are no-connects in the m28525. (1) sprxdata[1] a16 sprxdata[2] c15 sprxdata[3] b15 sprxdata[4] c10 sprxdata[5] b9 sprxdata[6] a8 sprxdata[7] d10 sprxdata[8] c2 sprxdata[9] e4 sprxdata[10] c1 sprxdata[11] d2 sprxdata[12] j1 sprxdata[13] k3 sprxdata[14] l4 sprxdata[15] k2 sprxdata[16] aa4 sprxdata[17] ab3 sprxdata[18] ae1 sprxdata[19] ad2 sprxdata[20] ae7 sprxdata[21] ad8 sprxdata[22] ac9 sprxdata[23] af7 sprxdata[24] af13 sprxdata[25] af14 sprxdata[26] ac14 sprxdata[27] ad14 sprxdata[28] ac18 sprxdata[29] ae20 sprxdata[30] af21 sprxdata[31] ad20 table 1-9. m28529 pin descriptions (8 of 19) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 28 mindspeed proprietary and confidential serial line interface sptxsync[0] frame sync input/ output a14 i/o when the ph y serial interface is enabled, this is the frame sync. sptxsync is input only for all port modes except dsl mode. in dsl mode, sptxsync is output only. note that ports 16?31 are no-connects in the m28525. (1) caution: some of the sptxsync pins become outputs when the device is configured for utopia-utopia mode. the designer is cautioned to ensure that phyint fcsel never gets configured low. sptxsync[1] a13 sptxsync[2] b13 sptxsync[3] c13 sptxsync[4] c8 sptxsync[5] b7 sptxsync[6] a6 sptxsync[7] c7 sptxsync[8] g4 sptxsync[9] f3 sptxsync[10] e1 sptxsync[11] f2 sptxsync[12] l1 sptxsync[13] m3 sptxsync[14] n5 sptxsync[15] m1 sptxsync[16] ac4 sptxsync[17] ad4 sptxsync[18] af2 sptxsync[19] af3 sptxsync[20] ae9 sptxsync[21] ad10 sptxsync[22] af9 sptxsync[23] ac11 sptxsync[24] ad15 sptxsync[25] af16 sptxsync[26] ae16 sptxsync[27] ac16 sptxsync[28] ae22 sptxsync[29] ac20 sptxsync[30] ad21 sptxsync[31] af24 table 1-9. m28529 pin descriptions (9 of 19) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 29 mindspeed proprietary and confidential serial line interface sptxdata[0] transmit line data output d13 o when the phy serial interface is enabled, this is the transmit line data output. note that ports 16?31 are no-connects in the m28525. (1) sptxdata[1] a12 sptxdata[2] e13 sptxdata[3] c12 sptxdata[4] d8 sptxdata[5] b6 sptxdata[6] a5 sptxdata[7] a4 sptxdata[8] h4 sptxdata[9] g3 sptxdata[10] f1 sptxdata[11] g2 sptxdata[12] n4 sptxdata[13] n3 sptxdata[14] n1 sptxdata[15] p1 sptxdata[16] ad5 sptxdata[17] ac6 sptxdata[18] ae4 sptxdata[19] af4 sptxdata[20] ae10 sptxdata[21] af10 sptxdata[22] ad11 sptxdata[23] ae11 sptxdata[24] ad16 sptxdata[25] ae17 sptxdata[26] af17 sptxdata[27] ac17 sptxdata[28] ae23 sptxdata[29] ac21 sptxdata[30] ad22 sptxdata[31] af25 table 1-9. m28529 pin descriptions (10 of 19) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 30 mindspeed proprietary and confidential serial line interface sptxclk[0] transmit line clock input a 15 i/pd when the phy serial interface is enabled, this is the transmit line clock input. note that ports 16?31 are no-connects in the m28525. (1) sptxclk[1] d14 sptxclk[2] c14 sptxclk[3] b14 sptxclk[4] c9 sptxclk[5] b8 sptxclk[6] a7 sptxclk[7] d9 sptxclk[8] f4 sptxclk[9] e3 sptxclk[10] d1 sptxclk[11] e2 sptxclk[12] k1 sptxclk[13] l3 sptxclk[14] l2 sptxclk[15] m4 sptxclk[16] ac3 sptxclk[17] ab4 sptxclk[18] af1 sptxclk[19] ae2 sptxclk[20] ae8 sptxclk[21] ad9 sptxclk[22] ac10 sptxclk[23] af8 sptxclk[24] af15 sptxclk[25] ae14 sptxclk[26] ac15 sptxclk[27] ab14 sptxclk[28] ac19 sptxclk[29] ae21 sptxclk[30] af22 sptxclk[31] af23 table 1-9. m28529 pin descriptions (11 of 19) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 31 mindspeed proprietary and confidential atm layer utopia interface atmutxaddr[0] atm utopia transmit address l23 i transmit atm cell bus address. atmutxaddr[1] k25 atmutxaddr[2] l24 atmutxaddr[3] k26 atmutxaddr[4] l25 atmutxdata[0] atm utopia transmit data e26 i transmit direction atm side cell data. atmutxdata[1] f25 i atmutxdata[2] h23 i atmutxdata[3] g24 i atmutxdata[4] f26 i atmutxdata[5] g25 i atmutxdata[6] h24 i atmutxdata[7] j23 i atmutxdata[8] g26 i/pd atmutxdata[9] h25 i/pd atmutxdata[10] j24 i/pd atmutxdata[11] k23 i/pd atmutxdata[12] h26 i/pd atmutxdata[13] j25 i/pd atmutxdata[14] k24 i/pd atmutxdata[15] j26 i/pd atmutxprty atm utopia transmit parity d26 i parity status signal. in 8 bit utopia mode, a parity calculation is performed over atmutxdata[7:0] for each clock cycle of atmutxclk. odd parity is used. in 16 bit utopia mode, this signal is the parity of atmutxdata[15:0]. this signal is optional. table 1-9. m28529 pin descriptions (12 of 19) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 32 mindspeed proprietary and confidential atm layer utopia interface atmutxclav[0] atm utopia transmit cell available g23 o/ts cell available signals for tran smit atm cells ( active high). when atmutxclav[1] or atmutxclav[0] is active one or more complete cells can be transferred from the atm layer. only atmutxclav[0] is used (atmutxclav[1] is ignored) when the dualclavenb (bit 4) is low (def ault) in the atmintfc register 0xf03. this is the most common configuration. atmutxclav[1] e25 atmutxsoc atm utopia transmit start of cell f24 i start of cell synchr onization signal for tran smit atm cells (active high). indicates that the first byte/word of the 53 byte cell is being placed on the atmutxdata bus. atmutxenb[0]* atm utopia transmit enable d25 i/pu data transfer enable(s) for transmit atm cells (active low). indicates that the first by te/word of the 53 byte cell is being placed on the atmutxdata bus. only atmutxenb[0] is used (atmutxenb[1] will be ignored) when the dualclavenb (bit 4) is low (default) in the atmintfc register 0xf03. this is most common configuration. when using single clav mode (dualclavenb bit is set to 0), atmutxenb[1] must be pulled up. atmutxenb[1]* c26 atmutxclk atm utopia transmit clock m23 i clock signal used for transfer of transmit atm cells from the atm layer. the maximum clock rate is 50 mhz (note: 33 mhz in tc only mode). atmurxsoc atm utopia receive start of cell c19 o/ts start of cell synchronization signal for receive atm cells (active high). indicates that the first byte/word of the 53 byte cell is being placed on the atmurxdata bus. atmurxclk atm utopia receive clock f23 i clock signal used for transfer of receive atm cells from the atm layer. the maximum clock rate is 50 mhz. (note: 33 mhz in tc only mode). atmurxclav[0] atm utopia receive cell available b20 o/ts cell available signals for r eceive atm cells (act ive high). when atmurxclav[1] or atmurxclaav[ 0] is active, one or more complete cells can be transferred to the atm layer. only atmurxclav[0] is used (atmurxclav[1] is ignored) when the dualclavenb (bit 4) is low (def ault) in the atmintfc register 0xf03. this is the most common configuration. atmurxclav[1] a21 atmurxenb[0]* atm utopia receive enable a20 i/pu enable data transfer and ou tput enable for receive atm cells (active low). when using single clav mode (dualclavenb, bit4 in atmintfc register 0xf03, is set low), only atmurxenb[0] is used and atmurxenb[1] is not used but must be pulled up. this is most common configuration. atmurxenb[1]* d18 table 1-9. m28529 pin descriptions (13 of 19) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 33 mindspeed proprietary and confidential atm layer utopia interface atmurxdata[0] atm utopia receive data c20 o/ts receive direction atm side cell data. atmurxdata[1] b21 atmurxdata[2] a22 atmurxdata[3] d20 atmurxdata[4] c21 atmurxdata[5] b22 atmurxdata[6] a23 atmurxdata[7] a24 atmurxdata[8] d21 atmurxdata[9] c22 atmurxdata[10] b23 atmurxdata[11] b24 atmurxdata[12] c23 atmurxdata[13] d22 atmurxdata[14] b25 atmurxdata[15] a26 atmurxprty atm utopia receive parity d19 o/ts parity status signal. in 8 bit utopia mode, a parity calculation is performed over atmurxdata[7:0] for each clock cycle of atmurxclk. odd parity is used. in 16 bit utopia mode, this signal is the parity of atmurxdata[15:0]. this signal is optional. atmurxaddr[0] atm utopia receive address e23 i receive atm cell bus address. this address determines the source channel of the receive at m cells output from the ima subsystem and also selects the ch annel sourcing the atmurxclav signal. all 5 bits are not required in every application. atmurxaddr[1] d24 atmurxaddr[2] c25 atmurxaddr[3] b26 atmurxaddr[4] e24 table 1-9. m28529 pin descriptions (14 of 19) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 34 mindspeed proprietary and confidential power supply vdd18 supply voltage (1.8 v) e9 e10 e17 j5 j22 k5 k10 k11 k16 k17 k22 l10 l17 t10 t17 u5 u10 u11 u16 u17 u22 v5 v22 ab9 ab10 ab17 ab18 power supply connections. (1.8 v) table 1-9. m28529 pin descriptions (15 of 19) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 35 mindspeed proprietary and confidential power supply vdd33 supply voltage (3.3 v) c18 c24 e7 e8 e11 e12 e15 e19 e20 g5 g22 h5 h22 k12 k15 l5 l22 m2 m5 m10 m17 m22 r10 r17 r22 t5 power supply connections. (3.3 v) power supply vdd33 (continued) supply voltage (3.3 v) (continued) t22 u3 u12 u15 w5 w22 y5 y22 ab7 ab8 ab11 ab12 ab15 ab16 ab19 ab20 ae3 power supply connections. (3.3 v) table 1-9. m28529 pin descriptions (16 of 19) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 36 mindspeed proprietary and confidential power supply vss ground a1 b2 b12 d17 d23 e5 e6 e14 e21 e22 f5 f22 k13 k14 l11 l12 l13 l14 l15 l16 m11 m12 m13 m14 m15 m16 ground connections. table 1-9. m28529 pin descriptions (17 of 19) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 37 mindspeed proprietary and confidential power supply vss (continued) ground (continued) n2 n10 n11 n12 n13 n14 n15 n16 n17 n22 p5 p10 p11 p12 p13 p14 p15 p16 p17 r11 r12 r13 r14 r15 r16 r25 t11 t12 ground connections. table 1-9. m28529 pin descriptions (18 of 19) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 38 mindspeed proprietary and confidential 1.5.2 pin diagram and definitions (utopia-to-utopia configuration) figures 1-9 and 1-10 illustrate the logic and block diagrams of the m2852x?s functional modu les. pin descriptions are listed in ta b l e 1-11 . figure 3-33 is the pinout diagram for the m28529 when operating in the utopia-to-utopia mode. it is a single cmos integrated circuit packaged in a 484-pin pbga. all unused input pins should be connected to ground or power. unused output and bidirectional pins should be left unconnected. power supply vss (continued) ground (continued) t13 t14 t15 t16 u13 u14 aa5 aa22 ab5 ab6 ab13 ab21 ab22 ac24 ad3 ae15 ground connections. vgg electrostatic discharge (esd) supply voltage ac23 d4 provides esd protection when inte rfacing with 5 v systems. if using this device in a system with 5 v logic, this pin must be connected to 5 v. if using 3.3 v system, connect to 3.3 v. spare spare pins a25 b1 aa23 ab23 ac05 ac25 spare (unused) pins on the package. reserved for future use and should be left unconnected. footnote: (1) all unused inputs should be tied to ground or left unconnected. all unused outputs or bidirecti onal pins should be left unco nnected. note: utopia-to-utopia configura tion is selected by tying the phyintfcsel pin low. when using the m28525/9 in utopia to utopia configuration, in addition to the standard utopia level 2 specification definitions, the device uses the phy side rx and tx clav signals for t he following purpose: - the phy tx clav signals are used to determine th e stuffing rate for sicp cells . the m28525/9 will monitor the clav signal to determine the fullness of the downstream device's utopia fifo. - for applications where timing is not available from the rx_trls (such as dsl), the m28525/9 can be configured to use the phy rx clav signals to generate a clock that approximates the payload timing. as such, the expectation is the rx clav signals from the tc/phy layer approximates an idea l phy layer device in the sense that cell boundary times present on the receive physical bus are reproduced with a fixed offset in time to the cells available on the phy utopia bus. contact mindspeed applications engineering for more details. table 1-9. m28529 pin descriptions (19 of 19) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 39 mindspeed proprietary and confidential figure 1-9. m28529 logic diagram (utopia-to-utopia) reset i reset* reset 8khzin clock i 8khzin* one second interface i/o one second input/output onesecio phy transmit clock o phy transmit enable o phy transmit address bus o i phy transmit cell available o phy transmit data bus o phy transmit start of cell phyutxclk phyutxenb[1:0]* phyutxaddr[4:0] phyutxclav[1:0] phyutxsoc phyutxdata[15:0] phyurxcl k phyurxenb[1:0]* phy utopia transmit interface phy utopia recei ve interface phy interface select i sync/async mode select i microprocessor clock i chip select i address strobe, write control i write/read read control i address bus i o status output o summary interrupt o ready i/o microprocessor data bus phyintfcsel (1) msyncmode mi cr ocl k mcs * mas*, mwr mw/r, mrd * microaddr[11:0] microprocessor interface test reset i test clock i test mode select i test data input i test enable i test mode i trst * tck tms tdi testenable testmode tdo jtag interface atm utopia transmit interface statout [1:0] microint * mrdy microdata[7:0] atm transmit clock i atm transmit enable i atm transmit address bus i atmutxclk atmutxenb[1:0] * atmutxaddr[4:0] o test dat a out put atmutxclav[1:0] atmutxsoc atmutxprty atmutxdata[15:0] o atm transmit cell available i atm transmit parity i atm transmit data bus atm utopia recei ve interface atmurxclk atmurxenb[1:0] * atmurxaddr[4:0] atm recei ve cl ock i atm receive enable i atm receive address bus i at murxsoc atmurxprty atmurxdata[15:0] o atm receive cell available o atm receive parity o atm recei ve data bus ima system clock i ima_sysclk ima_refclk ima reference clock i ima clocks txtrl[1:0] o transmit reference clock external memory interfac e memdata[15:0] memory data bus i/o extmemsel external memory select i memaddr[19:0] o memory address bus o chip enable memct r l _ce * o output enable memct rl _oe * o write enable memct r l _we * o sram cl ock memct rl _cl k memctrl_adsc* o address enable (1) pulled high i atm transmit start of cell o atm receive start of cell atmurxcl av[1:0] phy receive enable o phy receive address bus o phy recei ve cl ock o phyurxaddr[4:0] phyurxcl av[1: 0] phyurxsoc phyurxdata[15:0] i phy receive cell available i phy receive start of cell i phy recei ve dat a bus phyutxprty o phy transmit parity phyurxprty i phy receive parity
functional description 28529-dsh-001-k mindspeed technologies ? 40 mindspeed proprietary and confidential figure 1-10. ima block diagram table 1-10. utopia-to-utopia configuration information atmmux [7,6] (atmintfc, 0xf03) phyintfcsel (pin ad24) description 01 low ima utopia using the phy side utopia; internal tc block and serial ports not used. general note: use of exte rnal memory is optional. and passthrough and passthrough
functional description 28529-dsh-001-k mindspeed technologies ? 41 mindspeed proprietary and confidential table 1-11. m2852x pin descriptions (1 of 18) pin label signal name no. i/o description micro interface statout[0] status output ab24 o general pur pose output pins under software control. statout[1] ad26 msyncmode microprocessor synchronous/ asynchronous bus mode select ae24 i/pd selects synchronous or asynchronous bus mode, which determines the functions of two pins, mw/r, mrd* (pin w4) and mas*,mwr* (pin y2). a logic 1 selects the synchronous bus mode. in this mode, these pins are defined as follows: mw/r (w4) and mas* (y2). a logic 0 selects the asynchronous sram-type bus mode. in this mode, the pins are defined as follows: mrd* (w4) and mwr* (y2). reset* device reset t4 i/pu when asserted low, r esets the device. the microprocessor clock must be present before reset is released. if configuring the device for pass-through operation, a minimum delay of 25 us for ima_sysclk of 66 mhz or 33 us for ima_sysclk of 50 mhz is required from the release of r eset to the first access of the ima_rx_trans_table register or the ima_rx_atm_trans_table register (0x818/0x819). 8khzin 8 khz input ad25 i a clock input used to derive onesecio. typically operates at a frequency of 8 khz. onesecio one-second input/output ae26 i/o software can conf igure this pin as an output that equals the input from the 8khzin divided by 8000. when configured as an input, status registers and counters may be latched on the rising edge of this input. see bit 0 of the genctrl register (0xf00). mw/r, mrd* microprocessor write/ read w4 i when msyncmode is asserted high, this pin is a read/write control pin. in this mode, when mw/r is asserted high, a write access is enabled and the microdata[7:0] pin values will be written to the memory location indicated by the microaddr[11:0] pins. also, when mw/r is asserted low in this mode, a read access is enabled and the memory location indicated by the microaddr[11:0] pins is read. its value is placed on the microdata[7:0] pins. both read and write accesses assume the device is chip selected (mcs* = 0), the address is valid (mas* = 0), and the device is not being reset (reset* = 1). when msyncmode is asserted low, this pin is a read control pin. in this mode, when mrd* is asserted low, a read access is enabled and the memory location indicated by the microaddr[11:0] pins is read. its value is placed on the microdata[7:0] pins. mcs* microprocessor chip select v1 i when asserted low, the device is selected for read and write accesses. when asserted high, the device will not respond to input signal transitions on microclk , mw/r, mrd*, or mas*, mwr*. additionally, when mcs* is asserte d high, the microd ata[7:0] pins are in a high-impedance state but the microint* pin remains operational.
functional description 28529-dsh-001-k mindspeed technologies ? 42 mindspeed proprietary and confidential micro interface mas*, mwr* microprocessor address strobe y2 i when msyncmode is asserted high, this pin is an address strobe pin. when the mas* pin is asser ted low, it indicates a valid address, microaddr[ 11:0]. this signal is used to qualify read and write accesses. when msyncmode is asserted low, this pin is a write control pin. when mwr* is asserted low, a write access is enabled and the microdata[7:0] pin valu es will be written to the memory location indicated by the microaddr[11: 0] pins. the write access assumes the device is chip selected (mcs* = 0), a read access is not being requested (mrd* = 1), and the d evice is not bein g reset (reset* = 1). microaddr[0] microprocessor address bus u2 i these 12 bits are an address input for identifying the register to access. microaddr[1] t3 microaddr[2] u1 microaddr[3] t2 microaddr[4] r4 microaddr[5] t1 microaddr[6] r3 microaddr[7] r2 microaddr[8] p4 microaddr[9] r1 microaddr[10] p3 microaddr[11] p2 microdata[0] microprocessor data bus w3 i/o a bi-directional data bus for reading and writing data to internal registers. microdata[1] v4 microdata[2] y1 microdata[3] w2 microdata[4] v3 microdata[5] u4 microdata[6] w1 microdata[7] v2 microint* microprocessor interrupt request aa1 o when active low, the device needs servicing. it remains active until the pending interrupt is processed by the interrupt service routine. this pin is an open drain output for an external wired or logic implementation. an external pull-up resistor is required for this pin. table 1-11. m2852x pin descriptions (2 of 18) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 43 mindspeed proprietary and confidential micro interface mrdy microprocessor ready y3 o when active high, th e current read or writ e transaction has been completed. for a read transaction, the data is ready to be transferred to the microprocessor. for a write transaction, the data provided by the microprocessor has been written. this pin is an open drain output for an external wired or logic implementation. an external pull-up resistor is required for this pin. microclk microprocessor clock r5 i in asynchronous mode the microprocessor clock signal input can be clocked up to 66 mhz. in synchronous mode this pin can be clocked up to 25 mhz. the device samples the microprocessor interface pins (mcs*, mw/r, mrd*, mas*, microaddr[11:0], and microdata[7:0]) on the rising edge of this signal. the microprocessor interface output pins (microdata[7:0], microint*) are clocked on the rising edge of mi croclk. note that this clock is required for both synchronous and asynchronous operations. see note in section 1.15.1 . external memory extmemsel external memory enable ac26 i/pd when this pin is pulled high, it enables the external differential delay sram bus. memdata[0] differ ential delay memory data bus m26 i/o/pd differential delay sram data bus. atm cells extracted from the receive data stream are stored in the sram for the purpose of differential delay compensation. memdata[1] n24 memdata[2] n25 memdata[3] n26 memdata[4] p26 memdata[5] p25 memdata[6] p24 memdata[7] p23 memdata[8] r26 memdata[9] p22 memdata[10] r24 memdata[11] t26 memdata[12] r23 memdata[13] t25 memdata[14] t24 memdata[15] u26 table 1-11. m2852x pin descriptions (3 of 18) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 44 mindspeed proprietary and confidential external memory memaddr[0] differ ential delay memory address bus u25 o receive sram address bus. these signals are enabled by tying the extmemsel pin high. memaddr[1] t23 memaddr[2] v26 memaddr[3] u24 memaddr[4] v25 memaddr[5] w26 memaddr[6] u23 memaddr[7] v24 memaddr[8] w25 memaddr[9] y26 memaddr[10] v23 memaddr[11] w24 memaddr[12] y25 memaddr[13] aa26 memaddr[14] w23 memaddr[15] y24 memaddr[16] aa25 memaddr[17] y23 memaddr[18] ab26 memaddr[19] aa24 memctrl_ce* chip enable n23 o receive sram de vice select (active low) control signal. this signal is enabled by pulling the extmemsel pin high. memctrl_oe* output enable m25 o receive sram de vice output (active low) control signal. this signal is enabled by pulling the extmemsel pin high. memctrl_we* write enable m24 o receive sram wr ite enable (active low) control signal. this signal is enabled by pulling the extmemsel pin high. memctrl_clk sram clock ab25 o receive sram clock signal. this signal is enabled by pulling the extmemsel pin high. memctrl_adsc* address enable l26 o receive sram addr ess enable (active low) address strobe. this signal is enabled by pulling the extmemsel pin high. jtag trst* test reset c5 i/pu when asserted, the inte rnal boundary-scan logic is reset. this pin has a pull-up resistor. tck test clock a2 i/pu samples the value of tms and tdi on its rising edge to control the boundary scan operations. tms test mode select d5 i/pu controls the boundary-scan test access port (tap) controller operation. this pin has a pull-up resistor. tdi test data input c4 i/pu the serial test data input. this pin has a pull-up resistor. tdo test data output c3 o the serial test data output. table 1-11. m2852x pin descriptions (4 of 18) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 45 mindspeed proprietary and confidential test testenable[0] af26 i/pd factory t est use only, tie to vss. testenable[1] ac22 scanenable ad23 i/pd factory test use only, tie to vss tristate tristate ae25 i/pd when this pin is high, all outputs are tristate. phy side interface phyintfcsel phy interface select ad24 i/pu if this pin is tied low, the phy utopia interface mode is selected. this table shows pin configurations with this pin tied low. if this pin is tied high, the phy serial mode is selected. phyurxclk utopia receive clock af9 o ima_sysclk/2 phyurxenb[0]* phy utopia receive enable af16 o data transfer and output enable for receive phy ce lls (active low). to support multiple phy device s, separate enable signals are provided. depending on the software configuration, some of the enable signals may not be availa ble and will be replaced by additional phy cell bus address bits. when the phy size (bits 4 and 5) of register 0x804 are set to 2 (single clav), phyurxenb[1] must be pulled up. phyurxenb[1]* ad15 phyurxaddr[0] phy utopia receive address ae11 o receive phy cell bus address. the following limitations apply: phyurxaddr[1] ad11 phyurxaddr[2] af10 phyurxaddr[3] ae10 phyurxaddr[4] ac11 phyurxclav[0] phy utopia receive cell available af19 i/pd cell available signals for r eceive phy interfaces. phyurxclav[n] is active when one or more complete cells can be transferred. to support different phy devices, separate cell available signals are provided. this allows expansion to 32 points. phyurxclav[1] af18 i/pd table 1-11. m2852x pin descriptions (5 of 18) pin label signal name no. i/o description device addresses m28525 0?15, 31 m28529 0?31
functional description 28529-dsh-001-k mindspeed technologies ? 46 mindspeed proprietary and confidential phy side interface (continued) phyurxdata[0] phy utopia receive data ab14 i/pd received 16 bit phy cell data. all received cells are passed to the internal ima processor. phyurxdata[1] ac15 phyurxdata[2] ae14 phyurxdata[3] af15 phyurxdata[4] ad14 phyurxdata[5] ac14 phyurxdata[6] af14 phyurxdata[7] af13 phyurxdata[8] ae13 phyurxdata[9] ad13 phyurxdata[10] ac13 phyurxdata[11] af12 phyurxdata[12] ae12 phyurxdata[13] ad12 phyurxdata[14] af11 phyurxdata[15] ac12 phyurxsoc phy utopia start of cell ad17 i/pd start of ce ll synchronization signal for receive phy cells (active high). indicates that the first byte of the cell is being placed on the phyurxdata[7:0] bus. phyurxprty phy utopia receive parity ae18 i/pd odd parity calculated over phyurxdata[15:0] pins in 16-bit mode and over phyurxdata[7:0] pins in 8-bit mode. phyutxaddr[0] phy utopia transmit address g2 o transmit phy cell bus address. the follow ing limitations apply: phyutxaddr[1] f1 phyutxaddr[2] g3 phyutxaddr[3] h4 phyutxaddr[4] f2 phyutxclav[0] phy utopia transmit cell available e2 i/pd cell available signals for tran smit atm cells. when phyutxclav[n] is active high, the phy has space available for one or more complete cells. to support different phy devices, separate cell available signals are provided. phyutxclav[1] d1 phyutxclk phy utopia transmit clock g4 o ima_sysclk divided by two. table 1-11. m2852x pin descriptions (6 of 18) pin label signal name no. i/o description device addresses m28525 0?15, 31 m28529 0?31
functional description 28529-dsh-001-k mindspeed technologies ? 47 mindspeed proprietary and confidential phy side interface (continued) phyutxdata[0] phy utopia transmit data af4 o 8 bit phy cell data to be sent out the phy facility. 8 bit utopia interface used to transmit data to the external tc devices. phyutxdata[1] ae4 phyutxdata[2] ac6 phyutxdata[3] ad5 phyutxdata[4] af3 phyutxdata[5] af2 phyutxdata[6] ad4 phyutxdata[7] ac4 phyutxdata[8] p1 phyutxdata[9] n1 phyutxdata[10] n3 phyutxdata[11] n4 phyutxdata[12] m1 phyutxdata[13] n5 phyutxdata[14] m3 phyutxdata[15] l1 phyutxenb[0]* phy utopia transmit enable e1 o data transfer enable for transmit phy cells (active low signal). to support different phy devices, separate enable signals are provided. when the phy size (bits 4 and 5) of register 0x804 are set to 2 (single clav), phyutxenb[1] must be pulled up. phyutxenb[1]* f3 phyutxsoc phy utopia transmit start of cell ae9 o start of cell synchronization signal for transmit phy cells (active high). indicates that the first byte of a cell is being placed on the phyutxdata[7:0] bus. phyutxprty phy utopia transmit parity ad10 o odd parity calculated over phyutxdata[15:0] pins in 16-bit mode and over phyutxdata[7:0] pins in 8-bit mode. ima clocks ima_sysclk ima subsystem clock e18 i/pu most of the ima logi c circuits use this clock (o r a derivative of it). it can also be used as a t1/e1 reference clock. refer to section 1.12 . ima_refclk ima reference clock e16 i/pu if this is to be used as a reference clock, set the frequency as shown in section 1.12 . txtrl[0] transmit reference clocks a19 o transmit reference clocks. txtrl[1] b19 table 1-11. m2852x pin descriptions (7 of 18) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 48 mindspeed proprietary and confidential atm layer utopia interface atmutxaddr[0] atm utopia transmit address l23 i transmit atm cell bus address. atmutxaddr[1] k25 atmutxaddr[2] l24 atmutxaddr[3] k26 atmutxaddr[4] l25 atmutxdata[0] atm utopia transmit data e26 i transmit direction atm side cell data. atmutxdata[1] f25 i atmutxdata[2] h23 i atmutxdata[3] g24 i atmutxdata[4] f26 i atmutxdata[5] g25 i atmutxdata[6] h24 i atmutxdata[7] j23 i atmutxdata[8] g26 i/pd atmutxdata[9] h25 i/pd atmutxdata[10] j24 i/pd atmutxdata[11] k23 i/pd atmutxdata[12] h26 i/pd atmutxdata[13] j25 i/pd atmutxdata[14] k24 i/pd atmutxdata[15] j26 i/pd atmutxprty atm utopia transmit parity d26 i parity status signal. in 8 bit ut opia mode, a parity calculation is performed over atmutxdata[7:0] for each clock cycle of atmutxclk. odd parity is used. in 16 bit utopia mode, this signal is the parity of atmutxdata[ 15:0]. this signal is optional. table 1-11. m2852x pin descriptions (8 of 18) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 49 mindspeed proprietary and confidential atm layer utopia interface atmutxclav[0] atm utopia transmit cell available g23 o/ts cell available signals for tran smit atm cells (active high). when atmutxclav[1] or atmutxclav[0] is active one or more complete cells can be transferred from the atm layer. only atmutxclav[0] is used (atmutxclav[1] is ignored) when the dualclavenb (bit 4) is low (default) in the atmintfc register 0xf03. this is the most common configuration. atmutxclav[1] e25 atmutxsoc atm utopia transmit start of cell f24 i start of cell synchronization signal for transmit atm cells (active high). indicates that the first byte/word of the 53 byte cell is being placed on the atmutxdata bus. atmutxenb[0]* atm utopia transmit enable d25 i/pu enable data transfer enable(s) for transmit atm cells (active low). indicates that the first byte/word of the 53 byte cell is being placed on the atmutxdata bus. when using single clav mode (dualclavenb, bit4 in atmintfc register 0xf03, is set low), only atmutxenb[0] is used and atmutxenb[1] is not used but must be pulled up. this is most common configuration. atmutxenb[1]* c26 i/pu atmutxclk atm utopia transmit clock m23 i clock signal used for transfer of transmit atm cells from the atm layer. the maximum clock rate is 50 mhz. (note: 33 mhz for tc only mode.) atmurxsoc atm utopia receive start of cell c19 o/ts start of cell synchronization signal for receive atm cells (active high). indicates that the first byte/word of the 53 byte cell is being placed on the atmurxdata bus. atmurxclk atm utopia receive clock f23 i clock signal used for transfer of receive atm cells from the atm layer. the maximum clock rate 50 mhz. (note: 33 mhz for tc only mode.) atmurxclav[0] atm ut opia receive cell available b20 o/ts cell available signals for r eceive atm cells (active high). when atmurxclav[1] or atmurxclaav[ 0] is active, one or more complete cells can be transferred to the atm layer. only atmurxclav[0] is used (atmurxclav[1] is ignored) when the dualclavenb (bit 4) is low (default) in the atmintfc register 0xf03. this is the most common configuration. atmurxclav[1] a21 atmurxenb[0]* atm utopia receive enable a20 i/pu data transfer and output enab le for receive atm cells (active low). only atmurxenb[0] is used (atmur xenb[1] will be ignored) when the dualclavenb (bit 4) is low (d efault) in the atmintfc register 0xf03. this is most common configuration. when using single clav mode (dualclavenb bit is set to 0), atmurxenb[1] must be pulled up. atmurxenb[1]* d18 i/pu table 1-11. m2852x pin descriptions (9 of 18) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 50 mindspeed proprietary and confidential atm layer utopia interface atmurxdata[0] atm utopia receive data c20 o/ts receive direction atm side cell data. atmurxdata[1] b21 atmurxdata[2] a22 atmurxdata[3] d20 atmurxdata[4] c21 atmurxdata[5] b22 atmurxdata[6] a23 atmurxdata[7] a24 atmurxdata[8] d21 atmurxdata[9] c22 atmurxdata[10] b23 atmurxdata[11] b24 atmurxdata[12] c23 atmurxdata[13] d22 atmurxdata[14] b25 atmurxdata[15] a26 atmurxprty atm utopia receive parity d19 o/ts parity status signal. in 8 bit utopia mode, a parity calculation is performed over atmurxdata[7 :0] for each clock cycle of atmutxclk. odd parity is used. in 16 bit utopia mode, this signal is the parity of atmurxdata[15:0]. this signal is optional. atmurxaddr[0] atm utopia receive address e23 i receive atm cell bus address. this address determines the source channel of the receive atm cells output from the ima subsystem and also selects the channel sourcing the atmurxclav signal. atmurxaddr[1] d24 atmurxaddr[2] c25 atmurxaddr[3] b26 atmurxaddr[4] e24 table 1-11. m2852x pin descriptions (10 of 18) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 51 mindspeed proprietary and confidential power supply vdd18 supply voltage (1.8 v) e9 e10 e17 j5 j22 k5 k10 k11 k16 k17 k22 l10 l17 t10 t17 u5 u10 u11 u16 u17 u22 v5 v22 ab9 ab10 ab17 ab18 power supply connections. (1.8 v) table 1-11. m2852x pin descriptions (11 of 18) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 52 mindspeed proprietary and confidential power supply vdd33 supply voltage (3.3 v) c18 c24 e7 e8 e11 e12 e15 e19 e20 g5 g22 h5 h22 k12 k15 l5 l22 m2 m5 m10 m17 m22 r17 r10 r22 t5 power supply connections. (3.3 v) power supply vdd33 (continued) supply voltage (3.3 v) (continued) t22 u12 u15 w5 w22 y5 y22 ab7 ab8 ab11 ab12 ab15 ab16 ab19 ab20 ae3 u3 power supply connections. (3.3 v) (continued) table 1-11. m2852x pin descriptions (12 of 18) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 53 mindspeed proprietary and confidential power supply vss ground a1 b2 b12 d17 d23 e5 e6 e14 e21 e22 f5 f22 k13 k14 l11 l12 l13 l14 l15 l16 m11 m12 m13 m14 m15 m16 ground connections. table 1-11. m2852x pin descriptions (13 of 18) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 54 mindspeed proprietary and confidential power supply vss ground n2 n10 n11 n12 n13 n14 n15 n16 n17 n22 p5 p10 p11 p12 p13 p14 p15 p16 p17 r11 r12 r13 r14 r15 r16 r25 t11 t12 ground connections. power supply vss (continued) ground (continued) t13 t14 t15 t16 u13 u14 aa5 aa22 ab5 ab6 ab13 ab21 ab22 ac24 ad3 ae15 ground connections. (continued) vgg electrostatic discharge (esd) supply voltage ac23 d4 provides esd protection when interfacing with 5 v systems. if using this device in a system with 5 v logic, this pin must be connected to 5 v. if using 3.3 v system, connect to 3.3 v. table 1-11. m2852x pin descriptions (14 of 18) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 55 mindspeed proprietary and confidential power supply unused inputs a3 a7 a8 a9 a10 a11 a15 a16 a17 a18 b3 b4 b5 b8 b9 b10 b11 b14 b15 b16 b17 b18 c1 c2 c6 c9 c10 c11 c14 c15 c16 c17 d2 d3 d6 d7 d9 d10 d11 d12 d14 d15 d16 e3 e4 f4 g1 h1 h2 h3 j1 j2 unused inputs with internal pulldown table 1-11. m2852x pin descriptions (15 of 18) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 56 mindspeed proprietary and confidential power supply unused input j3 j4 k1 k2 k3 k4 l2 l3 l4 m4 y4 aa2 aa3 aa4 ab1 ab2 ab3 ab4 ac1 ac2 ac3 ac7 ac8 ac9 ac10 ac18 ac19 unused inputs with internal pulldown table 1-11. m2852x pin descriptions (16 of 18) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 57 mindspeed proprietary and confidential power supply unused input ad1 ad2 ad6 ad7 ad8 ad9 ad18 ad19 ad20 ae1 ae2 ae5 ae6 ae7 ae8 ae19 ae20 ae21 af1 af5 af6 af7 af8 af20 af21 af22 af23 unused inputs with internal pulldown table 1-11. m2852x pin descriptions (17 of 18) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 58 mindspeed proprietary and confidential power supply unused i/o a6 a13 a14 ac16 ac20 ad21 ae16 ae22 af24 b7 b13 c7 c8 c13 unused i/o with pulldown (outputs in tristate) note: leave unconnected. power supply unused outputs a12 ac17 ac21 ad16 ad22 ae17 ae23 af17 af25 b6 c12 d13 d8 e13 unused outputs (tristate) note: leave unconnected. spare spare a25 b1 aa23 ab23 ac5 ac25 spare (unused) pins on the package. reserved for future use and should be left unconnected. table 1-11. m2852x pin descriptions (18 of 18) pin label signal name no. i/o description
functional description 28529-dsh-001-k mindspeed technologies ? 59 mindspeed proprietary and confidential 1.5.3 interleaved hi ghway configuration four serial data streams can be combined together into one serial data stream using an interleaved highway interface. for more information on the operation of the interleaved highway, refer to section 1.14.2.5.5 . the interleaved highway interface can be enabled on a per highway basis. when an interleaved highway is enabled the pinout of the group of four muxed serial streams, see ta b l e 1-12 for the grouping, changes to the pinout desribed in ta bl e 1-14 , ta b l e 1-15 and ta bl e 1-16 . ta b l e 1-13 desribes the functionality of each of the interleaved highway interface pins. table 1-12. serial stream muxing into interleaved highway interleaved highway serial stream interleaved highway serial stream 00 4 16 1 17 2 18 3 19 14 5 20 5 21 6 22 7 23 28 6 24 9 25 10 26 11 27 312 7 28 13 29 14 30 15 31
functional description 28529-dsh-001-k mindspeed technologies ? 60 mindspeed proprietary and confidential table 1-13. m28529 interleaved highway pin descriptions pin label signal name i/o description interleaved hwy interface ihrxsync[x] interleaved highway receive frame sync input i/pd w hen the interleaved highway interface is enabled, this is the frame sync input. ihrxclk[x] interleaved highway transmit clock input i/pd whe n the interleaved highway interface is enabled, this is the receive line clock input. ihrxindo[x] interleaved highway receive timeslot indicator input i/pd when the interleaved highway interface is enabled, this is the receive timeslot indicator input. ihrxdata[x] interleaved highway receive data input i/pd whe n the interleaved highway interface is enabled, this is the receive line data input. ihtxsync[x] interleaved highway transmit frame sync input/output i/pd when the interleaved highway interface is enabled, this is the frame sync. ihtxclk[x] interleaved highway transmit clock input i/pd whe n the interleaved highway interface is enabled, this is the transmit line clock input. ihtxindo[x] interleaved hi ghway transmit timeslot indicator input i/pd when the interleaved highway interface is enabled, this is the transmit timeslot indicator input. ihtxdata[x] interleaved highway transmit data output o whe n the interleaved highway interface is enabled, this is the transmit line data output table 1-14. interleaved highway port 0 - 3 pinouts interleaved highway 0 interleaved highway 1 interleaved highway 2 interleaved highway 3 pin label no. pin label no. pin label no. pin label no. ihrxsync[0] b17 ihrxsync[1] c11 ihrxsync[2] b4 ihrxsync[3] h1 ihrxclk[0] b18 ihrxclk[1] a11 ihrxclk[2] b5 ihrxclk[3] g1 ihrxindo[0] a17 ihrxindo[1] b10 ihrxindo[2] d6 ihrxindo[3] k4 ihrxdata[0] d15 ihrxdata[1] c10 ihrxdata[2] c2 ihrxdata[3] j1 ihtxsync[0] a14 ihtxsync[1] c8 ihtxsync[2] g4 ihtxsync[3] l1 ihtxdata[0] d13 ihtxdata[1] d8 ihtxdata[2] h4 ihtxdata[3] n4 ihtxindo[0] a13 ihtxindo[1] b7 ihtxindo[2] f3 ihtxindo[3] m3 ihtxclk[0] a15 ihtxclk[1] c9 ihtxclk[2] f4 ihtxclk[3] k1
functional description 28529-dsh-001-k mindspeed technologies ? 61 mindspeed proprietary and confidential the interleaved highway can be selected on a per group of 4 channel basis. when interleaved highway mode is selected, the following serial mode pins, as identified in ta b l e 1-16 become unused. table 1-15. interleaved highway port 4 - 7 pinouts interleaved highway 4 interleaved highway 5 interleaved highway 6 interleaved highway 7 pin label no. pin label no. pin label no. pin label no. ihrxsync[4] y4 ihrxsync[5] ae6 ihrxsync[6] af12 ihrxsync[7] ad18 ihrxclk[4] aa2 ihrxclk[5] ae5 ihrxclk[6] ac12 ihrxclk[7] ad17 ihrxindo[4] aa3 ihrxindo[5] ad7 ihrxindo[6] ac13 ihrxindo[7] ae19 ihrxdata[4] aa4 ihrxdata[5] ae7 ihrxdata[6] af13 ihrxdata[7] ac18 ihtxsync[4] ac4 ihtxsync[5] ae9 ihtxsync[6] ad15 ihtxsync[7] ae22 ihtxdata[4] ad5 ihtxdata[5] ae10 i htxdata[6] ad16 ihtxdata[7] ae23 ihtxindo[4] ad4 ihtxindo[5] ad10 ihtxindo[6] af16 ihtxindo[7] ac20 ihtxclk[4] ac3 ihtxclk[5] ae8 ihtxclk[6] af15 ihtxclk[7] ac19 general note: 1. interleaved highway serial port 4-7 pins are no connects on the m28525. table 1-16. no connects per interleaved highway group (1 of 4) highway 0 a16 a18 b14 b15 b16 c14 c15 c16 c17 d14 d16 input no connects with pulldown b13 c13 unused i/o (pulled do wn/outputs tristate) note: leave unconnected. a12 c12 e13 unused outputs (tristate) note: leave unconnected.
functional description 28529-dsh-001-k mindspeed technologies ? 62 mindspeed proprietary and confidential highway 1 a7 a8 a9 a10 b8 b9 b11 d9 d10 d11 d12 unused input (pulled down) a6 c7 unused i/o (pulled dow n/outputs tristate) note: leave unconnected. a4 a5 b6 unused output (tristate) note: leave unconnected. highway 2 a3 b3 c1 c6 d1 d2 d3 d7 e2 e3 e4 unused input (pulled down) e1 f2 unused i/o (pulled dow n/outputs tristate) note: leave unconnected. f1 g2 g3 unused output (tristate) note: leave unconnected. highway 3 h2 h3 j2 j3 j4 k2 k3 l2 l3 l4 m4 unused input (pulled down) m1 n5 unused i/o (pulled dow n/outputs tristate) note: leave unconnected. n1 n3 p1 unused output (tristate) note: leave unconnected. table 1-16. no connects per interleaved highway group (2 of 4)
functional description 28529-dsh-001-k mindspeed technologies ? 63 mindspeed proprietary and confidential highway 4 ab1 ab2 ab3 ab4 ac1 ac2 ad1 ad2 ae1 ae2 af1 unused input (pulled down) af2 af3 unused i/o (pulled dow n/outputs tristate) note: leave unconnected. ac6 ae4 af4 unused output (tristate) note: leave unconnected. highway 5 ac7 ac8 ac9 ac10 ad6 ad8 ad9 af5 af6 af7 af8 unused input (pulled down) ac11 af9 unused i/o (pulled dow n/outputs tristate) note: leave unconnected. ad11 ae11 af10 unused output (tristate) note: leave unconnected. highway 6 ab14 ac14 ac15 ad12 ad13 ad14 ae12 ae13 ae14 af11 af14 unused input (pulled down) ac16 ae16 unused i/o (pulled dow n/outputs tristate) note: leave unconnected. ac17 ae17 af17 unused output (tristate) note: leave unconnected. table 1-16. no connects per interleaved highway group (3 of 4)
functional description 28529-dsh-001-k mindspeed technologies ? 64 mindspeed proprietary and confidential highway 7 ad19 ad20 ae18 ae20 ae21 af18 af19 af20 af21 af22 af23 unused input (pulled down) ad21 af24 unused i/o (pulled dow n/outputs tristate) note: leave unconnected. ac21 ad22 af25 unused output (tristate) note: leave unconnected. table 1-16. no connects per interleaved highway group (4 of 4)
functional description 28529-dsh-001-k mindspeed technologies ? 65 mindspeed proprietary and confidential 1.6 stand alone cell delineation figure 1-11 is an example of a non-ima application. the m28529 is being used as a stand alone cell delineator. cell delineation is performed internally and the m2852x interfaces directly to the framers. these framers could be t1/e1 or dsl. note: there may be applications that require the flexibility of the m28529 in a non-ima mode. this mode is also useful for troubleshoot during development since the ima block is bypassed. configuration information is shown in table 1-17 . figure 1-11. non-ima application table 1-17. cell delineation configuration information atmmux [7,6] (atmintfc, 0xf03) phyintfcsel (pin ad24) description 10 high tc block direct; d evice used as stand-alone cell delineator with 32 serial ports; ima block not used.
functional description 28529-dsh-001-k mindspeed technologies ? 66 mindspeed proprietary and confidential 1.7 source loopbacks (utopia-to-serial configuration only) source loopback checks that the host (the atm layer) is communicating with the phy. it is enabled and disabled in bit 5 of the pmode register (0x04). when source loopback is enabled for a given port, all data transmitted by the m2852x on that port is also looped back through the receive line interface. data from the framer interface is ignored. there are two different modes of source loopback, source loopback mode 0 and source loopback mode 1. the loopbacks work in tc enabled modes. 1.7.1 source loopback mode 0 during source loopback mode 0, the port is automatically placed in general purpose mode and an internal clock (ima_sysclk/2 for ima mode, atmutxclk for tc only mode) is used as the clock to loop back cells. as a result of the automatic mode switch and clock used, the data on the tx serial lines will be corrupted. 1.7.2 source loopback mode 1 during source loopback mode 1, the port is not placed in general purpose mode (the serial framing remains as configured) and the sptxclk and sptxsync device input signals are routed along with the sptxdata to the tc receive port circuit. figure 1-12. source loopback diagram (for simpli city the diagram shows the tc block only.) atm cell transmitter tc transmit port 4-cell fifo tc receive port atm cel l recei ver cel l alignment cell validation vpi/vci screening 4-cell fifo host interface transmit utopi a level 2 host interface recei ve utopi a level 2 framer (line) interface sptxclk loopback control this segment is replicated for ports 0-31 sptxsync sptxdata utopia level 2 interface atmutxclk atmutxclav atmutxenb* atmutxsoc atmutxdata[15:0] atmutxprty atmutxaddr[4:0] atmurxcl k atmurxcl av atmurxenb* atmurxsoc atmurxdata[15:0] atmurxprty atmurxaddr[4:0] * see note * sptxdata will be corrupted in in source loopback mode 0
functional description 28529-dsh-001-k mindspeed technologies ? 67 mindspeed proprietary and confidential 1.8 far-end line loopback (serial configuration only) far-end line loopback verifies line interface is communic ating with the phy. it is enabled by bit 4 of the pmode register (0x04). when line loopback is enabled for a given port, all data received by the m2852x on that port is processed by the receive line interface and transmitted out the line interface. data from the transmit utopia bus is ignored. note: sptxclk, sprxclk, sptxsync, and sprxsync must be present for the loopback mode to function properly for a given port. figure 1-13. far-end line loopback (this only shows the tc block.) utopia level 2 interface ima interface transmit utopia level 2 atmutxclk atmurxclk loopback control atm cell transmitter tc transmit port ima interface receive utopia level 2 sptxdata sptxclk sptxsync atmutxclav atmutxenb* atmutxsoc atmutxprty atmutxaddr[4:0] atmurxclav atmurxenb* atmurxprty atmurxaddr[4:0] sprxdata sprxclk sprxsync sprxhold atmurxdata[15:0] atmutxdata[15:0] tc receive port this segment is replicated for ports 0 - 7 atm cell receiver cell alignment cell validation vpi/vci screening 4-cell fifo 4-cell fifo framer (line) interface 500027_058 atmurxsoc general note: configuring a port for line loopback mode disables all utopia signals for that port.
functional description 28529-dsh-001-k mindspeed technologies ? 68 mindspeed proprietary and confidential 1.9 ima line loopback ima line loopback is provided as shown in figure 1-14 . this loopback occurs in the phy layer utopia interface of the ima block. the loopback is functional both when the serial/interleaved (tc enabled) is selected and when the phy side utopia interface (tc bypass) is selected. wh en this loopback is selected, incoming receive data continues through the ima processor and is looped back out of the transmit interface. 1.10 ima system loopbacks ima system loopback is provided as shown in figure 1-15 . this loopback occurs in the phy layer utopia interface in the ima block. when this loopback is selected, incoming transmit system data is looped back after ima processing and continues out the phy side interface. t he loopback is functional regardless of which phy side interface mode is selected. there are two different modes of system loopback, ima system loopback 0 and ima system loopback 1. 1.10.1 ima system loopback 0 during ima system loopback 0, data is looped back at the phy layer ul2 interface. the txclav signals from the phy (tc or external) are used for handshaking and data is passed through the tc block to the serial interface (if the tc block is enabled) or is routed to the phy side utopia interface (if the tc block is disabled). figure 1-14. ima line loopback p h y l a y e r u t o p i a 2 i n t e r f a c e ima engine line interface 0 c o n t r o l r e g i s t e r s ima clocks tc status registers tc control registers micro interface pins tc counters t x f i f o r x f i f o a t m l a y e r u t o p i a 2 i n t e r f a c e t x f i f o r x f i f o micro clocks m i c r o c l k i 8 k h z i n o n e s e c i o s t a t u s r e g i s t e r s jtag a t m l a y e r u t o p i a i n t e r f a c e p i n s p h y s i d e i n t e r f a c e p i n s internal 512kx8 sram external memory interface pins extmemsel pin differential delay memory interface i p h y i n t f c s e l p i n s e r i a l / i n t e r l e a v e d m o d e e n a b l e d u t o p i a m o d e e n a b l e d t c b l o c k u t o p i a i n t e r f a c e i m a b y p a s s e n a b l e d i m a a n d t c e n a b l e d i m a b y p a s s e n a b l e d l o w h i g h i m a a n d t c e n a b l e d 1 0 c l o c k i n t e r f a c e onesec rx block and passthrough tx block and passthrough ima tc ports i m a _ s y s c l k t x t r l [ 0 ] t x t r l [ 1 ] cell processor line interface 1 cell processor line interface 30 cell processor line interface 31 cell processor ... i m a _ r e f c l k atm-side interface phy-side interface ext ram interface jtag interface micro interface
functional description 28529-dsh-001-k mindspeed technologies ? 69 mindspeed proprietary and confidential 1.10.2 ima system loopback 1 during ima system loopback 1, data is looped back at the phy layer ul2 interface, but the txclav signals are ignored from the phy layer. data is not passed through the tc block during this mode. 1.11 reference designs please contact mindspeed for information on reference designs and schematic examples. 1.12 ima clocks ima frame rates must be locked to the phy payload rates (the bandwidth reserved for atm cells) used by those phy ports designated as ima timing reference links. this applies to both the transmit and receive directions. ima frame rates can be derived from a number of sources: ima_sysclk fixed divide-by-24 or programmable divider ima_refclk figure 1-15. ima system loopback p h y l a y e r u t o p i a 2 i n t e r f a c e ima engine line interface 0 c o n t r o l r e g i s t e r s ima clocks tc status registers tc control registers micro interface pins t c counter s t x f i f o r x f i f o a t m l a y e r u t o p i a 2 i n t e r f a c e t x f i f o r x f i f o micro clocks m i c r o c l k i 8 k h z i n o n e s e c i o s t a t u s r e g i s t e r s jta g a t m l a y e r u t o p i a i n t e r f a c e p i n s p h y s i d e i n t e r f a c e p i n s internal 512kx8 sram external memory interface pins extmemsel pin differential delay memory interface i p h y i n t f c s e l p i n s e r i a l / i n t e r l e a v e d m o d e e n a b l e d u t o p i a m o d e e n a b l e d t c b l o c k u t o p i a i n t e r f a c e i m a b y p a s s e n a b l e d i m a a n d t c e n a b l e d i m a b y p a s s e n a b l e d l o w h i g h i m a a n d t c e n a b l e d 1 0 c l o c k i n t e r f a c e onese c rx block and passthrough tx block and passthrough ima tc ports i m a _ s y s c l k t x t r l [ 0 ] t x t r l [ 1 ] cell processor line interface 1 cell processor line interface 30 cell processor line interface 31 cell processor ... i m a _ r e f c l k atm-side interface phy-side interface ext ram interface jtag interface micro interface during ima system loopback 0 data will flow through the tc block to the serial interface if enabled. duing ima system loopback 0, if utopia-utopia mode is selected, the txclav signals will be used for handshaking and data will flow to the phy side utopia interface.
functional description 28529-dsh-001-k mindspeed technologies ? 70 mindspeed proprietary and confidential line rate clock input or programmable divider sprxclk or ihrxclk phy line/payload rate clock rx phy side cell stream phy payload rate derived (synthesized) from cell transfer rate across phy side utopia interface it should be noted that the ima frame rates can not be directly derived from the sptxclk[31:0] inputs. in a typical application (see case 1 in ta bl e 1-18 ), the tx direction is referenced from local cloc k sources whereas the rx direction is slaved to the fe tx. it is also quite common (case 2 in ta bl e 1-18 ) for the tx direction to be slaved to the fe tx, often using the same source as the rx direction. in some rarer applications, (case 3 in ta bl e 1-18 ) both the tx and rx directions are referenced from local clock sources. internally the ima engine generates a transmit data cell rate clock (tx idcr) to match the exact cell rate of each group in the transmit side of the ima device. the ima engi ne also generates a receive data cell rate clock (rx idcr) to match receive cell rate for each group and operates the receive cell smoothing buffer. there is a tx idcr and rx idcr for each of the 32 groups that the m28529 supports. the m28529 also provides two clock outputs: tx_trl[1] and tx_trl[0]. these can be used to output one of the reference clock inputs or generate an 8 khz reference that is phase locked to im a_sysclk or ima_refclk (whichever is used as a timing reference). figure 1-16 shows the details of the m28529's ima clock block from figure 1-1 . this block is responsible for generating all clocks required by the ima engine. it can be further divided into 8 sections, as shown in ta b l e 1-19 : table 1-18. reference clock configurations / sources tx direction rx direction case configuration possible sources configuration sources 1 master / internal ima_sysclk ima_refclk slave / external sprxclk or ihrxclk rx cell stream ima_sysclk or ima_refclk (1) 2 slave / external sprxclk or ihrxclk rx cell stream ima_sysclk or ima_refclk slave / external sprxclk or ihrxclk rx cell stream ima_sysclk or ima_refclk 3 (2) master / internal ima_sysclk ima_refclk master / internal ima_sysclk ima_refclk footnotes: (1) these sources provide a ?last resort? clock in case no valid timing can be deri ved from rx side sources. (2) this case assumes the fe tx is loop timed to the ne tx; this will limit applications. it is also applicable in loopback test ing.
functional description 28529-dsh-001-k mindspeed technologies ? 71 mindspeed proprietary and confidential table 1-19. ima block clock sections clock section description serial port synchronizer this block contains a transition det ector and a synchronizer. it sync hronizes the clocks from the tc bl ock serial ports to the ima_sysclk divided by 16 and the rate multiplier (rm). it handles all 32 internal serial ports independently. the rate multiplier is configured to values 1, 2, or 4 based on the range of the link rate. ima_sysclk dividers this block contains two dividers: a divide by 16, a divide by 24, and divide by rate multiplier (rm). the di vide_16 is used to synchronize external clocks to internal logic. the divi de_24 allows the ima_sysclk to be used to generate both the rx idcr and the tx idcr clocks (provide d that ima_sysclk is 24 times the bit rate). ima_refclk synchronizer this block contains a transition detector and a synchronizer. it synchronizes the ima_refclk to the ima_ sysclk divided by 16 and the rm factor. idcr source mux this software controlled mu x selects which clock sources are feed to the appropriate idcr clock dividers. rx idcr clock this block divides the bit rate clock down to a link cell data rate clock based on the values of frame length (m), number of links in the group (n), frame payload (p) and frame bit (f ), then adjusts based on the rate multiplier (rm). (the 2048/ 2049 factor results from the ima standards requirement of inserting a stuff event every 2048 cells.) this block can generate 16 independent rx idcr clock outputs (one per group). tx idcr clock this block divides the bit rate clock down to a link cell data rate clock based on the values of frame length (m), number of links in the group (n), frame payload (p) and frame bit (f ), then adjusts based on the rate multiplier (rm). (the 2048/ 2049 factor results from the ima standards requirement of inserting a stuff event every 2048 cells.) this block can generate 16 independent rx idcr clock outputs (one per group). bit rate clock generator this block generates a clock that represen ts the link data rate. it can generate 16 independent tx and 16 independent rx clocks. in normal operation, all parameters are configured auto matically by the software dri ver. it contains the following blocks: pre-scaler?this block divides the selected input (either ima_ refclk or ima_sysclk) by th e factor of pnum divided by pden. synchronizer?synchronizes the pre-scaler output to the internal logic using the ima_sysclk divided by 16 and the rm factor. numerically controlled osci llator?this clock circuit generates the link bit rate. digital phase locked loop this block generates a bit rate clock that is phase locked to the phy side rxclav signal. it can monit or all 32 ports on the bus. any port can be selected as the group timing reference.
functional description 28529-dsh-001-k mindspeed technologies ? 72 mindspeed proprietary and confidential figure 1-16. m28529 clock diagram ima_sysclk divider n * rm (53 * 8) m-1 m p/f 2048 2049 n*8khz nco note 2 n*8khz nco note 2 synchronizer /16 r m 424 phase comparator /24 synchronizer transition detector pre-scaler 1 r m transition detector synchronizer 1 r m 1 r m n*8khz nco up/down adjust digital pll ref ref ref serial port synchronizer bit rate clk generator sprxclk 0 ima_refclk ima_sysclk ima_refclk synchronizer 1 r m idcr clk mux note 1 note 1 rx idcr clk note 3 n * rm (53 * 8) m-1 m p/f 2048 2049 tx idcr clk note 3 idcr clk mux general notes: 1. sprxclk 1-31 are identical but not shown for clarity 2. nco - numerically controlled oscillator, controlled by parameters in registers 0x816 and 0x817. 3. m- frame length. p - payload length (for example t1 = 192). f - frame length (for example t1 = 193). rm - rate multiplier. rxclav transition rx idcr clock tx idcr clock r x mux tx mux
functional description 28529-dsh-001-k mindspeed technologies ? 73 mindspeed proprietary and confidential 1.12.1 ima link rates in addition to supporting standard t1/e1 bit rates, the m2852x devices support fractional t1/e1 and dsl rates from 64 kbps to more than 8.192 mbps. the actual nominal link rate must be configured through software parameters. section 1.12.2.2 discusses the input clock requirements. when operating the device with only a single link rate used for all ima groups, any link rate within the specified range is possible. a reference clock synchronous with that link rate must be provided to the device. for multi-rate applications, internal timing generators (includes the synthesizers) within the device must be supplied a reference clock with sufficient accuracy and resolution to generate the required bit rates. the following relationship between link rate and ima_sysclk frequency exists: as an example, if ima_sysclk is 49.152 mhz, the link ra te boundaries occur at 3.072 mbps and 6.144 mbps. the maximum ima link rate is given by ima_sysclk/4, or 12.288 mbps. when using the internal bit rate clock generator, the resolution boundaries and maximum link rate are a function of the ?intermediate? frequency (output of the prescalar) selected. the ?intermediate? frequency is a function of the frequency of the input reference clock (ima_sysclk or ima_refclk) and the resolution of the prescalar (8 bits). this ?intermediate? frequency (int_freq) is limited to ima_sysclk/16 due to internal synchronization. at this limit, the values of ta b l e 1-21 apply. but it is also likely that the ?i ntermediate? frequency will be lower than ima_sysclk/16 and th e following applies: returning to the example of ima_sysclk = 49.152 mhz, if int_freq = 2.56 mhz, then the rate boundaries occur at 2.56 mbps and 5.12 mbps, with a maximum link rate of 10.24 mbps. 1.12.2 clock input requirements the system designer must select the frequencies of im a_sysclk and ima_refclk such that the ima core can process the aggregate cell bandwidth (bw), sample the serial clocks, and the ima frame rates can be derived. 1.12.2.1 aggregate cell bandwidth the maximum aggregate cell bandwidth requirement (rule of thumb) is a function of th e frequency of ima_sysclk and the number of active ima groups. the following are empirically determined limits when operating with 1 or more ima groups: 32 ima groups: maximum aggregate bw (mbps) < frequency of ima_sysclk (mhz) * (20 / 9). 16 ima groups maximum aggregate bw (mbps) < frequency of ima_sysclk (mhz) * (24 / 9). table 1-20. link rate resolution for variable rate applications (direct serial clock) link rate < ima_sysclk/16 ima_sysclk/16 < link rate < ima_sysclk/8 link rate > ima_sysclk/8 link rate n x 8 kbps n x 16 kbps n x 32 kbps table 1-21. link rate resolution for variable ra te applications (internal bit rate generator) link rate < int_freq int_freq < link rate < int_freq/2 link rate > int_freq/2 link rate n x 8 kbps n x 16 kbps n x 32 kbps
functional description 28529-dsh-001-k mindspeed technologies ? 74 mindspeed proprietary and confidential 1 ima group maximum aggregate bw (mbps) < frequency of ima_sysclk (mhz) * (28 / 9). if only pass-throughs are enabled, then the aggregate cell bandwidth limitation is: maximum aggregate bw (mbps) < frequency of ima_sysclk (mhz) * (16 / 5) ta bl e 1-22 list some examples. as an example, setting ima_sysclk = 49.152 mhz constr ains the maximum aggregate bw to be less than 152.9 mbps for configurations with at least 1 ima group. for a 32 port application, depending on the number of active ima groups, this implies a maximum aggregate bw in the range of 109.2 - 152.9 mbps with an average link bw in the range of 3.41 - 4.78 mbps. as another example, for a 16 port application, with 16 ima groups, the average link bw would be limited to 8.192 mbps (131.1 mbps / 16). this average link rate woul d increase if less than 16 ima groups were active. 1.12.2.2 serial clock sampling ima_sysclk is also used to sample the serial receive clocks (sprxclk) and ima_refclk. these sampled signals are used for ima frame rate generation. when operating with the interleaved highway interface enabled, the 4x input clock (ihrxclk) is first divided by 4 before being distributed to the ima block where it is sampled. if the serial interface is operating in fractional t1/e1 mode, either directly or using the interleaved highway interface, the resulting ?gated? clock being routed over to the ima core is not used. the requirements of the sprxclk, ihrxclk, and ima_refclk inputs are summarized below: table 1-22. maximum aggregate bandwidth examples ima_sysclk # ports # groups maximum bw (mbps) 49.152 mhz 1-32 0 157.3 1-32 1 152.9 1-32 16 131.1 1-32 32 109.2 66 mhz 1-32 0 211.2 1-32 1 205.3 1-32 16 176.0 1-32 32 146.7
functional description 28529-dsh-001-k mindspeed technologies ? 75 mindspeed proprietary and confidential 1.12.2.3 clock generator reference the internal clock generators and synthesizers operate in the ima_sysclk domain but are referenced from either the ima_sysclk or ima_refclk input. due to internal syn chronization circuitry, the following restriction applies to the ima_refclk input when it is used as a reference for these generators: frequency of ima_refclk > frequency of ima_sysclk / 16 1.12.3 summary examples the preceding sections listed many constraint s on the ima_sysclk and ima_refclk inputs. ta b l e 1-24 provides some simplified (and conservative) examples for these two clock signals. table 1-23. ima serial clock requirements interface clock period (1) ima link rate signal mode maximum minimum maximum (2) sprxclk t1/e1/dsl 256 / ima_sysclk 4 / ima_sysclk min (4 / ima_sysclk, int_freq / 4) ft1/fe1 n/a n/a int_freq / 4 ihrxclk t1/e1 n/a, f = 8.192 mhz 1.920 mbps ft1/fe1 n/a n/a 2.048 mbps ima_refclk (3) all 256 / ima_sysclk 16 / ima_sysclk ima_sysclk / 16 footnotes: (1) clock period is shown since the samp ling circuit is sensitive to the interval between rising edges of the clock signal. (2) limit is a function of whether bit rate generator is used. if not us ed, then ima_sysclk caps the link rate. if used, the int ermediate frequency (int_freq) determines the maximum link rate with the requirement that int_freq ima_sysclk / 16. (3) ima_refclk used as a line rate reference; in this case, ima_ refclk is not used as a reference for the internal bit rate gene rator.
functional description 28529-dsh-001-k mindspeed technologies ? 76 mindspeed proprietary and confidential 1.12.4 typical clock configurations 1.12.4.1 serial mode (using internal tc) figure 1-17 and figure 1-18 show simplified applications that utilize the serial interfaces and internal tc block of the m28529 device. the block labeled ?clock selection? in each figure may take on many forms depending on the clock configuration / sources and spec ific capabilities of the liu and fram er devices used in a given system application. 1.12.4.1.1 t1/e1 configurations in the most common t1/e1 application (shown in figure 1-17 ), t1/e1 line rate clocks and ima_sysclk are used to provide timing references. the m28529 device has internal dividers that generate the proper phy payload rates (1.536 mbps / 1.920 mbps) necessary for ima frame generation. since the line rate clocks are accessible within the m28529 device and all facilit ies operate at the same nominal rate, although they may be asynchronous, no programmable clock dividers or synthe sizers tend to be used in these app lications. asynchrono us facilities are allowed in independent transmit clock (itc) mode and are accommodated using the ima stuffing mechanism. table 1-24. ima reference clock summary examples phy interface ima_sysclk ima_refclk type mode # ports ref? (1) requirements ref? requirements t1/e1 serial 32 yes t1: 37.056 mhz e1: 49.152 mhz opt. t1: 1.544 mhz e1: 2.048 mhz no t1: 36.23 mhz (typical liu) (2) e1: 48.06 mhz (typical liu) yes t1: 1.544 or 1.536 mhz (3) e1: 2.048 or 1.920 mhz dsl serial 24 yes n x 8 khz, 40.96 mhz (4) n/a > 24 n x 8 khz, 49.152 mhz 24 no 40.96 mhz yes n x 8 khz, 4.64 mhz > 24 49.152 mhz t1/e1/ dsl utopia 24 yes n x 8 khz, 40.96 mhz n/a > 24 n x 8 khz, 49.152 mhz 24 no 40.96 mhz yes n x 8 khz, 4.64 mhz > 24 49.152 mhz footnotes: (1) indicates whether the clock signal is used as a timing reference. (2) frequency determined based on sa mpling sprxclk as described in section 1.12.2.2 . (3) a line or payload rate cloc k signal may be used. a payload ra te can only be used if all possi ble references (e .g., sprxclk) are also payload rate clocks. (4) 40.96 mhz is selected as a minimu m frequency for g.shdsl applications.
functional description 28529-dsh-001-k mindspeed technologies ? 77 mindspeed proprietary and confidential in the fractional t1/e1 application, the n x 64 kbps link rates are usually supported by relying on the programmable dividers and clock synthesizers within the m28529 device rather than reliance on the serial clocks themselves. the clock reference for these dividers and synthesizers is ei ther ima_sysclk or ima_ref clk. whichever input is being used, it must be an integer multiple of 8 khz. for ima_sysclk, the same 24x frequency as shown in figure 1-17 can be used but any frequency in the range of 33 - 66 mhz is permissible, subject to the restrictions discussed in section 1.12.2 . 1.12.4.1.2 dsl configurations the dsl application is similar to the fractional t1/e1 in the sense that the serial clocks are not often used directly as timing references. the link rates are usually set within the dsl transceiver as a programmable derivative of the ?system clock? provided to that device. in some cases, an 8 khz network timing reference (ntr) signal affects the generated rate. for the ima frame rates to be locked when operating in the ?master / internal? configuration, the m28529 and the dsl transceivers must have clocks that are derived from the same source. often, this is a simple matter of connecting the dsl system clock to the ima_refclk pin or using the ima_sysclk signal as the source of the dsl system clock. the ?slave / external? configuration usually relies on the clock synthesizers. figure 1-17. typical t1/e1 configurations liu framer 24x oscillator ima_sysclk 37.056 mhz (t1) or 49.152 mhz (e1) sprxclk[0] sptxclk[0] t1/e1 liu framer t1/e1 1x clock source ima_refclk 1.544 mhz (t1) or 2.048 mhz (e1) 32 sprxclk[31] sptxclk[31] 32 clock selection tx_trl[1:0] m28529 1.544 mhz (t1) or 2.048 mhz (e1)
functional description 28529-dsh-001-k mindspeed technologies ? 78 mindspeed proprietary and confidential 1.12.4.2 utopia mode the utopia mode applications are similar to the serial mo de but the serial clocks are not typically used (or always available). in utopia mode, the m28529 device only has the sprxclk[23:0] inputs available for those applications that can take advantage of them. as noted, these aren?t typically used. 1.12.4.2.1 t1/e1 configurations the t1/e1 utopia application is shown in figure 1-19 . it is similar to figure 1-17 with the tc blocks external to the m28529 device. since the device does not provide 32 se rial clocks, the ima function most often is configured to use its internal clock synthesizers when operating in the ?slave / external? configuration. this approach is used when operating in fractional t1/e1 applications. figure 1-18. serial dsl configurations i/f dsp local oscillator ima_sysclk 33 - 66 mhz sprxclk[0] sptxclk[0] dsl dsl ima_refclk 32 sprxclk[31] sptxclk[31] 32 clock selection tx_trl[0] m28529 framer ntr i/f dsp framer ntr dsl system clock 8 khz ntr source dsl clock
functional description 28529-dsh-001-k mindspeed technologies ? 79 mindspeed proprietary and confidential 1.12.4.2.2 dsl configurations since the serial clocks are not typically used as timing re ferences when operating in dsl applications, the utopia mode configurations are similar to the serial mode configurations. figure 1-20 shows the dsl utopia application. figure 1-19. t1/e1 configurations (utopia mode) figure 1-20. dsl configurations (utopia mode) liu framer 24x oscillator ima_sysclk 37.056 mhz (t1) or 49.152 mhz (e1) t1/e1 liu framer t1/e1 1x clock source ima_refclk 1.544 mhz (t1) or 2.048 mhz (e1) clock selection tx_trl[1:0] m28529 1.544 mhz (t1) or 2.048 mhz (e1) tc tc sprxclk[0] sprxclk[23] i/f dsp local oscillator ima_sysclk 33 - 66 mhz dsl dsl ima_refclk 32 32 clock selection tx_trl[0] m28529 framer ntr i/f dsp framer ntr dsl system clock 8 khz ntr source dsl clock tc tc phy rx utopia phy tx utopia
functional description 28529-dsh-001-k mindspeed technologies ? 80 mindspeed proprietary and confidential the solution for high port count and variable rate dsl a pplications is to use inter nal counters and frequency synthesizers referenced from a common (n x y khz) clock input with feedback from the cell available signal from the phy side utopia bus. for low port count, single rate applications that take advantage of the embedded atm cell processor, the use of receive bit clock inputs is the most straight-forward solution. 1.12.5 ima internal timing examples 1.12.5.1 t1/e1 using internal serial ports 1.12.5.1.1 using ima_sysclk as the transmit clock figure 1-21 illustrates t1/e1 with internal serial ports, using ima_sysclk equal to 24 times the line rate. this is one of the simplest implementations of ima when a clock equal to 24 times the line rate is available. several issues are worth noting: the ima_refclk input is unused and should be tied to ground. the m28529 is deriving all required clocks from the serial port clocks and the ima_sysclk. the ima_sysclk is used to synchroni ze the sprxclk inputs to internal logic (via the divide by 16 block). the sprxclk is being used to generate the rx idcr cloc k. also note that the receiv e clock from any link within a group could be used to generate the rx idcr for that group. the ima_sysclk is being used to derive the tx idcr clock. the device is configured using a software driver. the following code is an example of calls to the driver: ima_link_type = ima_ds1 ima_dsl_use_ref_clk2 = ima_inactive ima_dsl_ref_generator = ima_inactive ima_alt_rx_trl = ima_inactive ima_grp_tx_trl_src = ima_ref_xclk (grp#) ima_grp_rx_trl_src = ima_rx_trl_(x) (grp#)
functional description 28529-dsh-001-k mindspeed technologies ? 81 mindspeed proprietary and confidential 1.12.5.1.2 using ima_refclk as the transmit clock figure 1-22 illustrates t1/e1 with internal serial ports, using ima_refclk. there are seve ral important differences from the first example: in this case, ima_sysclk is only used by internal logic. it must be greater than or equal to 22 times the line rate to ensure that internal logic can keep up with the data. again, the sprxclk is used to generate the rxidcr clock. the tx idcr clocks are generated from the ima_refclk. thus ima_refclk must equal 1.544, 1.536, 2.028, or 1.920 mhz depending of the frame format used. the device is configured using a software driver. the following code is an example of calls to the driver: figure 1-21. t1/e1 using internal serial ports; ima_sysclk equals 24x line rate n*8khz nco note 2 n*8khz nco note 2 synchronizer /16 rm 424 phase comparator synchronizer transition detector pre-scaler 1 rm transition detector synchronizer 1 rm 1 rm n*8khz nco up/down adjust ref ref 1 rm note 1 note 1 general notes: 1. sprxclk 1-31 are identical but not shown for clarity 2. rm - rate multiplier. /24 sprxclk 0 ima_refclk not used; tie to ground ima_sysclk 24 x line rate rx mux tx mux txclav transition ref
functional description 28529-dsh-001-k mindspeed technologies ? 82 mindspeed proprietary and confidential ima_link_type = ima_ds1 ima_dsl_use_ref_clk2 = ima_inactive ima_dsl_ref_generator = ima_inactive ima_alt_rx_trl = ima_inactive ima_grp_tx_trl_src = ima_ref_clk1 (grp#) ima_grp_rx_trl_src = ima_rx_trl_(x) (grp#) 1.12.5.2 dsl/t1/e1 using ut opia-to-utopia interfaces figure 1-23 illustrates the configuration most commonly used with applications that require more the tc block to be external. up to 32 links and 32 groups can be supported us ing external cell delineators. for the discussion below, assume the link rates are less than 3.072 mbps. figure 1-22. t1/e1 using internal seri al ports; ima_refclk equals line rate n*8khz nco note 2 n*8khz nco note 2 synchronizer /16 rm 424 phase comparator synchronizer transition detector pre-scaler 1 rm transition detector synchronizer 1 rm 1 rm n*8khz nco up/down adjust ref ref ref 1 rm idcr clk mux note 1 note 1 tx mux general notes: 1. sprxclk 1-31 are identical but not shown for clarity 2. rm - rate multiplier. /24 sprxclk 0 ima_refclk ima_sysclk 24 x line rate rx mux txclav transition ref
functional description 28529-dsh-001-k mindspeed technologies ? 83 mindspeed proprietary and confidential the rx idcr clock is synthesized using the rxclav inpu t from the phy side utpoia bus. this is performed on a per group basis; that is, one link in each group is selected (via software) to provide the rx idcr for that group. ima_sysclk must be greater than or equal to 40.96 mhz (less than 24 ports) and be greater than or equal to 49.152 mhz if there are more than 24 ports. either ima_sysclk or ima_refclk can be used as the tx idcr clock: ima_sysclk may be used if it is an 8 khz multiple of the bit rate. ima_refclk may be used if it is an 8 khz multiple of the bit rate and greater than or equal to 4.64 mhz. the device is configured using a software driver. the following code is an example of calls to the driver: ima_link_type = ima_var_rate ima_dsl_ref_clk_frequency = 40960000 ima_dsl_use_ref_clk2 = ima_inactive ima_dsl_ref_generator = ima_active ima_alt_rx_trl = ima_active ima_grp_link_bandwidth = 2304 (grp#) ima_grp_clk_ref_factor = ima_no_div (grp#) ima_grp_tx_trl_src = ima_ref_xclk (grp#) ima_grp_rx_trl_src = ima_rx_trl_(x) (grp#)
functional description 28529-dsh-001-k mindspeed technologies ? 84 mindspeed proprietary and confidential 1.13 utopia interfaces the m2852x supports multi-phy operation as described in the utopia level specification (af-phy-0039.000, see www.atmforum.com ). this standard allows up to 31 ports to be interfaced to both the atm and phy side interfaces. the interfaces use either 8-bit or 16-bit wide data buses, and cell-level handshaking. each of the m2852x's utopia blocks have two sections, transmit and receive. for the atm interface, on the transmit side, atm cell data is placed in the transmit fifos where it can then be passed to the atm cell processing block. on the receive side of the utopia interface, incoming cells are placed in the receive fifo until sent. both fifos on the atm side are 4 cells deep. figure 1-23. dsl?utopia-to-utopia n*8khz nco note 2 n*8khz nco note 2 synchronizer /16 rm 424 phase comparator synchronizer transition detector pre-scaler 1 rm transition detector synchronizer 1 rm 1 rm n*8khz nco up/down adjust ref ref ref 1 rm note 1 note 1 tx mux general notes: 1. sprxclk 1-31 are identical but not shown for clarity 2. nco - numerically controlled oscillator; controlled by parameters in register 816 and 817. 2. rm - rate multiplier. /24 sprxclk 0 ima_refclk ima_sysclk 24 x line rate rx mux txclav transition
functional description 28529-dsh-001-k mindspeed technologies ? 85 mindspeed proprietary and confidential with regard to ima, each ima group is considered one logical port and will only take up one utopia address. for example, a group with 8 t1 links could be assigned to address 0; the ima engine handles the translation between the atm layer and the physical links. in addition, each pass-though connection also requires one address. to provide maximum flexibility for system design the m28529 has 3 utopia le vel 2 interface modes. this allows the m28529 to be used in either utopia-to-utopia or utopia-to-serial ima applications or it can function as a stand-alone cell delineator block. these interfaces are shown in figure 1-26 and described below. 1. ima direct?this interface allows the atm layer to interface directly to the ima engine. this would be the normal mode for all ima applications. it is controlled by registers in the ima section. 2. tc block direct?this interface is se lected when the ima engine is disabled and the device is being used as a stand-alone cell delineator. it may also be invoked during troubleshooting to verify serial port operation without having to run the ima drivers. it is configured by registers in the tc section. 3. phy side utopia?this interface is selected when the tc block is disabled and the designer wishes to interface to a device via an utopia interface. this allows the m28529 ima engine to address up to 32 ports on the line side. 1.13.1 general utopia operation three primary functions are performed by the utopia controller: pollin g, selection, and data transfer. these functions are basically the same for both the transmit and receive sides of the utopia bus. the following example describes the transmit functions. refer to figure 1-24 . the atm layer utopia controller polls the connected phy ports by transmitting the port addresses on the utxaddr lines. if a port is ready to tr ansfer data, it asserts ut xclav. note that the process of polling a port does not result in that port being selected to transfer data! polling allows the controller to determine which port is ready for data; it must then select that port before sending data. it does so by reasserting the desired address and then asserting utxenb*. the phy will then be ready to transfer data on the utxdat a lines. utxenb* is deasserted when the transfer is completed. polling can continue during the data transfer proc ess but not during port selection. it operates independently of the state of utxenb*. to pause the data transfer, utxenb* can be deasserted. to continue the transfer, the controller must reselect the port by transmitting its address one clock cycle before asserting utxenb*. the controller must ensure that the cell transfer from this port has been completed, to avoid a start-of-cell error. on the atm side, the utopia interface is a slave. on the phy side, the utopia interface is a master. 1.13.2 utopia 8-bit and 16-bit bus widths (phy and atm) the atm side utopia interface on the m2852x devices have two bus width options, 8-bit or 16-bit, depending on the selection of atmbuswidth, bit 5, of the atmintfc register (0xf03). the phy side utopia interface also has two bus width options 8-bit or 16-bit, depending on the selection of phybuswidth, bit 5, of the phyintfc register (0xf02). the protocols and timing are the same in both modes, except that 8-bit mode uses only the lower half of the data bus (txdata[7:0] and rxdata[7:0]) and odd parity is on ly generated or checked over those bits. the atm-side utopia level 2 interface operates up to 50 mhz in 16 bit mode (note: 33 mhz for tc mode only) and 33 mhz in 8 bit mode. the phy-side utopia interface operates at half the ima_sysclk rate (ima_sysclk/2) note: by convention, data being transferred from the phy to the atm layer is considered received data, while data from the atm layer to the phy is called transmitted data.
functional description 28529-dsh-001-k mindspeed technologies ? 86 mindspeed proprietary and confidential in 8-bit mode, each atm cell consists of 53 bytes. the first five bytes are used for header information. the remaining bytes are used for payload. in 16-bit mode, the cell consists of 54 bytes. the first five bytes contain header information. the sixth byte, udf2, is required to maintain alignment but is not read by the m2852x. the remaining bytes are used for payload. 1.13.3 utopia interface blocks 1.13.3.1 ima utopia this is the normal interface for ima applications and is selected as shown in ta bl e 1-25 . it is intended to interface to a single atm laye r device and appear as a multi-port phy device. figure 1-24 illustrates the connections to/from the atm layer device. th e number of ?ports? or c hannels on the ima subsystem is the sum of the number of configured ima groups plus the number of pass- through facilities. the ima m28529 requires a unique utopia address for each channel (ima group or pass-through). there are no restrictions placed on the address assignment and not all 32 locations are normally used. in ima utopia mode, the utopia interface can operate with single clav/enb or dual clav/enb handshaking. the default configuration is for single clav/enb handshaki ng (see register 0xf03 atmintfc for more information). when operated in single clav/enb mode, the utopia bus address 0x1f can be configured as a valid port address and not a null address, note this is nonstandard from the utopia specification and must be supported by connective devices. when using dual clav/enb mode, clav0/enb0 are assigned to addresses 0x0 - 0xf while clav1/enb1are assigned to addresses 0x10 - 0x1f. note that only the first 4 bits [3:0] of the 5 bit address bus are used internally, bit 4 is ignored. for example, if clav is supposed to be active for addresses 0x1 and 0x11, polling with address 0x1 on the address bus will cause clav0 to be asse rted and clav1 to be asserted. if only one channel is programmed, (a single ima group and no pass-through facilitie s), then the m28529 can be compatible with utopia level 1 by fixing the address lines to a specific value and setting the ima group?s atm address (through the software driver) to that value. the m28529 provides numerous options to match non-standard utopia controllers. see the ima_atm_utopia_bus_ctl register, 0x813, for more information. note: dual clav/enb does not allow multiple m28529 devices to interface with a single atm layer device on the atm-side utopia interface. multiple m28529 devices cannot share one utopia bus with an atm-layer device. note: in single clav mode, address 0x1f can be assigned as a valid port address to enable 32 unique addresses. the behavior of clav when a port is not selected can be set to eith er driven low or tri-state. see the ima_atm_utopia_bus_ctl register, 0x813, bit 1.
functional description 28529-dsh-001-k mindspeed technologies ? 87 mindspeed proprietary and confidential 1.13.3.2 tc block utopia this interface is selected when using the device as a stand-alone cell delineator. see ta b l e 1-25 and section 1.6 . it interfaces to the atm layer as a normal utopia level 2 interface with the following enhancements. udf2 programmability the user can program the contents of the udf2 byte wh en operating in 16-bit utopia mode. by default, the contents of the udf2 byte on the re ceive interface will match the default value of the utopia port address. this can be changed by writing the desired value to the corr esponding udf2 control register, 0x0f. bus width is controlled by bit 5 of the atmintfc register. port number assignment the utopia address for each port is stored in bits 0?4 of the utop2 register (0x0e). the default for this value is the port number. for example, the utop2 register for port 4 (0x10e [with the offset]) defaults to 04 hex. however, the value can be changed to any value from 00?1e hex by programming the register to accommodate multiple devices on the same utopia bus. the value 1f hex is re served for the null address. the utopia address should be changed only when the device or port is in the reset state. hec override in normal operation, the hec is calculated by the tc layer and put in byte 5, udf1. this may be overridden by setting bit 7 of the cgen register (0x08) to a 1. in this case, data inserted by the atm layer into byte 5 is transmitted unchanged by the device. figure 1-24. atm layer utopia interface connections table 1-25. device configuration options atmmux [7,6] (atmintfc, 0xf03) phyintfcsel (pin ad24) description 01 low ima utopia using the phy side utopia; utopia-to-utopia; tc block/serial ports not used. 01 high ima utopia using internal tc block; utopia-to-serial mode; 32 internal serial ports 10 high tc only; device used as stand-alone cell de lineator with 32 serial ports; ima block not used. m28529 phy layer utopia bus atmutopia tx data/ address bus atmutxclav_0 atmutxenb_0 atmutxclav_1 atmutxenb_1 atm layer device note: only transmit side drawn for clarity
functional description 28529-dsh-001-k mindspeed technologies ? 88 mindspeed proprietary and confidential in tc block utopia mode, both single and dual clav/enb modes are supported, however the single clav/enb mode only supports 31 addresses. utopia address 0x1f is a null address. in dual clav/enb mode, the device can respond as 32 unique phy devices (by sharing the same address but using different clav/enb?s), however address 0x1f is still a null address. 1.13.3.3 phy-side utopia an atm forum compliant utopia interface is provided for interfacing to phy layer devices. several unique features should be noted: 1. it is only utopia level 2. 2. this bus supports 8-bit and 16-bit wide data paths. 3. the utopia interface has a second set of control lines (dual clav/enb), which allow up to 32 atm devices to be connected to the bus. these can be connected as shown in figure 1-25 . this effectively provides two buses with up to 16 devices each, all sharing common address and data lines but with separate control lines. (remember, utopia uses address 0x1f as the null address thus limiting the bus to 31 ports. however, the standard also allows for multiple clav and enable lines.) 4. when using only a single clav/enb the device can be programmed to recognize null address 0x1f as a valid address. note that the tc block does not support 0x1f as an address. thus when using the utopia-serial configuration, dual clav/enb must be used if 32 ports are desired. figure 1-25. m28529 multiple utopia control lines 500027_056 cx28985 utopia port 8 ? 15 general note: cx28985 utopia port 0 ? 7 cx28985 utopia port 8 ? 15 cx28985 utopia port 0 ? 7 atm layer utopia bus m28529 utopia data/ address bus phyutxclav_1 phyutxenb_0 phyutxenb_1 phyutxclav_0 only the transmit side is shown for clarity. the receive side is identical. 1 8 9 16 17 24 25 32 ima link number
functional description 28529-dsh-001-k mindspeed technologies ? 89 mindspeed proprietary and confidential 1.13.4 dual clav/enb operation the utopia level 2 specification allows for 31 unique addresses 0-30 to be assigned to devices on the utopia bus. utopia address 31 is a null address. while both the atm and phy side utopia support the null address assigned as a valid address, many connecting devices ma y not support this. to alleviate this, the dual clav/enb mode is available to support all 32 po rts. when using dual clav/enb, the ut opia port will respond to either clav0/ enb0 or clav1/enb1 depending on the port. for the atm side, clav0/enb0 is assigned to port 0 - 15 and clav1/ enb1 is assigned to port 16-32. enabling of dual clav/enb mode for the atm side is set in the atmmintfc 0xf03 register. for the phy side, assignment of ports to clav/ enb is configurable in the ima_misc_config register 0x804. 1.14 transmission convergence block the m2852x?s atm transmission convergence (tc) block is responsible for recovering cell alignment using the hec octet, performing detection/correction, and descrambling the payload octets. the resulting atm cells are then passed to the atm layer via the utopia interface. simultaneously, the atm transmitter block is receiving data from the atm layer, optionally inserting header fields, opti onally calculating the hec, and sending the cells to the framers. if no data is being received from the atm layer, the cell processor generates idle cells based on the data programmed into the associated registers. 1.14.1 atm cell transmitter the atm cell transmitter controls the generation and formatting of 53-octet atm cells that are sent to the framer (line) transmit ports. this block formats an octet stre am containing atm data cells from the atm layer device when those cells are available. all 53 octets of the data cells may be obtained from the external data source and formatted into the outgoing octet stream. this block calculates the hec octet in the outgoing cell from the header field. the calculated hec octet can be inserted in place of the incoming data octet by writing dishec (bit 7) in the cgen register (0x08) to a logic 0. for testing purposes, this hec octet can be corrupted by xo ring the calculated value with a specific error pattern input set in the errpat register (0x0b). this hec error is achieved by writing errhec (bit 4) in the cgen register (0x08) to a logic 1. the remaining 48-octet payload field of the outgoing cell is obtained from the external data source. the payload can be scrambled. when there is no data from the atm layer device, the tc block inserts idle cells automatically in the outgoing octet stream. the 4-octet header field for these idle cells comes from the txidl1?4 registers (0x14?17). the hec octet is calculated and inserted automatically. the payload field is filled with the octet contained in the idlpay register (0x0a). in normal operation, the 4-octet header field in the outgoing cell is passed on from the atm layer device. header patterns can be modified in the txhdr1?4 registers (0x10?13) and inserted into outgoing cells in place of header bytes received from the atm layer. whether the original header cells or replacement cells are sent is controlled by bits 0?4 in the hdrfield (0x09) register. 1.14.1.1 hec generation in normal operation, the m2852x calculates the hec for the four header bytes of each cell coming from the atm layer. it then adds the hec coset (55 hex, by atm standards) and inserts the result in octet 5 of the outgoing cell. hec calculation can be disabled by setting bit 7 of cgen (0 x08) to a 1. when hec is disabled, the m2852x leaves the contents of the hec field unchanged and transmits whatever data is placed in that field by the atm layer. note: when operating in the utopia-to-utopia mode , the atm cell processor block is disabled.
functional description 28529-dsh-001-k mindspeed technologies ? 90 mindspeed proprietary and confidential the hec coset is used to maintain a valu e other than zero in the hec field. if the first four bytes in the header are zero, the hec derived from these bytes is also zero. when this occurs and there are strings of zeros in the data, the receiver cannot determine cell boundaries. therefore, it is recommended that the value 55 hex be added to the hec before transmission. to enable the hec coset on the transmit side, set bit 6 in register cgen (0x08) to one. to enable the receive hec coset, set bit 5 in register cval (0x0c) to one. 1.14.2 atm cell receiver the atm cell receiver performs cell delineation on incoming data cells by searching for the position of a valid hec field within the cell. the hec coset can be either active or inactive; this is determined in bit 5 in the cval (0x0c) register. 1.14.2.1 cell delineation the atm block receives octets from the framers and recovers atm cells by means of cell delineation. cell delineation is achieved by aligning atm cell boundaries using the hec algorithm. four consecutive bytes are chosen and the hec value is calculated. the result is co mpared with the value of the fo llowing byte. this ?hunt? is continued by shifting this four-byte window, one byte at a time, until the calculated hec value equals the received hec value. when this occurs, a pre-sync state is declared and the next 48 bytes are assumed to be payload. the atm block calculates hec on the four bytes following this payload, assuming that a new cell has begun. if seven figure 1-26. details of the tc block utopia level 2 interface ima transmit utopia level 2 atmutxclk atmurxclk microprocessor interface loopback control one second interface interrupt control atm cell transmitter tc transmit port ima receive utopia level 2 microint* microaddr[10:0] microdata[7:0] control lines sptxdata sptxclk sptxsync atmutxclav atmutxenb* atmutxsoc atmutxprty atmutxaddr[4:0] atmurxclav atmurxenb* atmurxprty atmurxaddr[4:0] tck 8khzin onesecio trst* tms tdi tdo sprxdata sprxclki sprxsync atmurxdata[15:0] atmutxdata[15:0] tc receive port this segment is replicated for ports 0 - 7 jtag controller status and control statout[0:1] atm cell receiver cell alignment cell validation vpi/vci screening 4-cell fifo 4-cell fifo framer (line) interface 500027_063 atmurxsoc
functional description 28529-dsh-001-k mindspeed technologies ? 91 mindspeed proprietary and confidential consecutive header blocks are found, synchronization is declared. if any hec calculation fails in the pre-sync state, the process begins again (see figure 1-27 ). synchronization will be held unt il seven consecutive incorrect hecs are received. at this time, the ?hunt? state is reinitiated. during the sync state of cell delineation, cells are passed to the utopia interface if the hec is valid. if a single-bit error in the header is detected, the error is corrected (optionally), and the cell is passed to the utopia interface. if hec checking is enabled and hec correcting is disabled (bit 3 in the cval register [0 x0c]), cells wit h single-bit hec errors are discarded. if a multi-bit error is detected, the cell is dropped. once either type of error is noted, all subsequent errored cells are dropped until a valid cell is received. this rule applies even for single-bit errors that could be corrected. once a valid cell is detected, the process begins again. (see figure 1-28 .) when loss-of-cell delineation (locd) occurs, an interrupt is generated and the m2852x automatically enters the ?hunt? mode. however, the cell is still being scrambled by the far-end transmit ter, leaving only the headers (or just the hec byte in distributed sample scrambler [dss]) unscrambled. this means that the only repetitive byte patterns in the data stream that meet the cell delineation criteria are valid headers (or just the hec bytes in dss). figure 1-27. cell delineation process pre-sync 7 errored hecs 6 correct hecs 1 errored hec 1 correct hec sync hunt 500027_006
functional description 28529-dsh-001-k mindspeed technologies ? 92 mindspeed proprietary and confidential when the m2852x is in general purpose mode, a synchroniz ation pulse from the framer interface is not always available. in this mode, the m2852x performs a bit seri al search to find byte and cell alignment. the m2852x selects a starting window of 32 sequential bits and ca lculates the hec over this window. this hec is then compared to the next eight incoming bits. if they do not match, the m2852x shifts the 32-bit window by 1 bit and recalculates the hec until a valid hec position is found. once byte-alignment is achieved, cell delineation is performed. 1.14.2.2 cell delineation control modes the m28529 contains two independent ?hec check? state machines. the cell delineator (cd) state machine is used to find cell delineation and, conv ersely, to declare loss of cell delineati on (locd). the othe r is the cell valid (cv) state machine, which is used to validate the cells to pass to the utopia fifos. these state machines are controlled by two register bits, (cval register, 0x0c), that allow the m28529 to be programmed for special applications. ta b l e 1-26 shows the control bits function. figure 1-28. header error check process cell delineation in sync state apparent multi-bit error (drop cell) apparent single-bit error (correct error and pass cell) no errors detected (pass cell) correction mode detection mode no errors detected (pass cell) errors detected (drop cell) 500027_007
functional description 28529-dsh-001-k mindspeed technologies ? 93 mindspeed proprietary and confidential 1.14.2.3 cell screening the m2852x provides two optional types of cell screening. the first type, idle cell rejection, prevents idle cells from being passed on. the second type, user traffic screening, compares incoming bits to the values in the receive cell header registers. cells are rejected or accepted based on the bit patterns of their headers. idle cell rejection is enabled in bit 6 of the cval register (0 x0c). if this bit is set to 1, all incoming cells that match the contents of the receive idle cell header control registers, rxidl1?4 (0x20?23), are rejected. individual bits in the receive idle cell mask control registers, idlmsk1?4 (0x24?27), can be set to 1 or don?t care, causing the corresponding bits of the incoming cell to be treated as matc hing, regardless of their value. if idle cell rejection is disabled, cells pass directly to user traffic screening. user traffic cell screening is similar to idle cell screening in that the inco ming cells are compared to the receive cell header control registers, rxhdr1?4 (0x18?1b). individual bits in the receive cell mask control registers, rxmsk1?4 (0x1c?1f), can be set to 1 or don?t care, causing the corresponding bits of the incoming cell to be treated as matching, regardless of their values. the rejhdr bit (bit 7) in the cval register (0x0c) determines whether matching cells are rejected or accepted. if it is set to 0, matching cells are accepted. if it is set to 1, matching cells are rejected. see ta bl e 1-27 and ta b l e 1-28 . table 1-26. control bit functions dislocd dishecchk description 0 0 normal operation; used for standard atm traffic. cells are output to the utop ia fifo only after cell de lineation is found. only ce lls with valid hecs are passed (this includes cells with single bit errors that have been corrected). 0 1 ignore hec errors mode; used for ima applications. the cell delineator state machine is active and looking for valid atm ce lls. it will follow the atm forum?s cell delineation process. howe ver, since the cell valid state machin e is turned off, the m28529 will pass all cells, including those with hec errors, to the utopia fifos. the m28529 will not transf er cells during locd. 1 0 the cell delineation functi on is disabled and every 53 bytes of in coming data is treated as a ?cell?. how- ever, since the cv machine is still active, only cells with valid hecs will be output. as a result, almost all data will be dropped. occasionally, random data will have what appears to be a valid hec and will be out- put. mindspeed is not aware of any use for this mode. 1 1 raw data mode; allows the m28529 to be used as a generic ?serial to parallel? convertor. all data received will be passed across the utopia bus in blocks of 53 bytes. no attempt is made to find atm cells. general note: 1. the hec error correction circui t is independent of th e dishecchk control bit. the m28529 will correct single bit errors even when the dishecchk is enabled (assuming that the enheccor bit is set to 1).
functional description 28529-dsh-001-k mindspeed technologies ? 94 mindspeed proprietary and confidential 1.14.2.4 cell scrambler the atm standard requires cell scrambling to ensure that only valid headers are found in the cell delineation process. scrambling randomizes any repeated patterns or other data strings that could be mistaken for valid headers. the m2852x supports two types of scrambling as defined by itu-t i.432: 1. self synchronizing scrambler (sss) 2. distributed sample scrambler (dss). typically, sss is used and is, therefore, th e m2852x?s default method. however, xdsl in asynchronous format generally use dss. 1.14.2.4.1 sss scrambling sss scrambling uses the polynomial 43 + 1 to scramble the payload, leaving the five header bytes untouched. it can be enabled in entxcellscr, bit 5, of the cgen register (0x08). descrambling uses the same polynomial to recover the 48-byte cell payload. it can be enabled in enrxcellscr, bit 4, of the cval register (0x0c). 1.14.2.4.2 dss scrambling dss scrambling uses the 31 + 28 + 1 polynomial to scramble the entire cell, except the hec byte. hec is calculated after the first four bytes of the header have been scrambled. dss scrambling is enabled in entxdssscr, bit 1, of the cgen register (0x08). descrambling uses the first six bits of the hec for alignment. once alignment is found, all eight bits of the hec are sampled. descrambling uses the same polynomial to recover the 48-byte cell payload. it is enabled in enrxdssscr, bit 0, of the cgen register (0x08). if dss descrambling fails, the m2852x defaults to unscrambled mode. table 1-27. cell screening?matching receive cell mask bit receive cell header bit incoming bit result 000match 001fail 010fail 011match 1xxmatch table 1-28. cell screening?accept/reject cell cell reject header result match 0 accept cell match 1 reject cell fail 0 reject cell fail 1 accept cell note: if both sss and dss are enabled, sss overrides dss.
functional description 28529-dsh-001-k mindspeed technologies ? 95 mindspeed proprietary and confidential 1.14.2.5 framing modes (utopi a-to-serial configuration) the m2852x?s 32 serial ports can be individually configured for the major framing modes: t1/e1, fractional t1/e1 and dsl. a general purpose framing mode provides an interface to customized framers and each of the 32 ports can be configured for a different mode. the m2852x also supports an interleaved highway mode where a combination of four t1, e1, fractional t1 or fractional e1?s can be transported over a higher bandwith 8.192 mhz interface. 1.14.2.5.1 t1/e1 interface this describes the timing requirements of the m28529 when operating in t1 or e1 mode. connection to a cn8370 t1/e1 framer is used as an example, as illustrated in figure 1-29 . the m28529 receives a t1/e1 data stream from the external framer, ignores the t1/e1 overhead, extracts the atm cells, and passes the atm cells to the atm layer device. in the transmit direction, the m28529 inserts 0?s in the overhead bit lo cations and fills the rest of the frame with atm cells from the utopia bus. for the e1 mode, the atm cells are mapped into time slots 1?15 and 17?31 as described in recommendation g.804 . for the t1 mode, the atm cells are mapped into time slots 1?24. note: dss scrambling is only supported in general purpose mode. figure 1-29. cn8370 interface diagram note: the 8370 is a single port transceiver which is shown here for simplicity. cn8370 transmit framer receive framer tpcmi tfsync rfsync rpcmo rsbcki, tsbcki m28529 tx frame marker serial data rx frame marker serial data clock sptxsync sptxdata sprxsync sprxdata sptxclk, sprxclk clock source
functional description 28529-dsh-001-k mindspeed technologies ? 96 mindspeed proprietary and confidential figure 1-30. cn8370 interface - t1 timing diagram lsb f msb 1.544 mhz clock tx framer marker tx serial data ts1 ts24 0 192 t1 mod count lsb f msb rx framer marker rx serial data ts1 ts24 0 192 t1 mod count general notes: in t1, atm cells are mapped into time slots 1-24
functional description 28529-dsh-001-k mindspeed technologies ? 97 mindspeed proprietary and confidential 1.14.2.5.2 fractional t1/e1 interface the purpose of the fractional t1/e1 logic is to gate off the serial clocks during inactive timeslots. the fractional t1/ e1 logic is enabled on a link-by-link basis when in serial mode or on all four links when the interleaved highway mode is enabled. figure 1-32 shows an example of fractional t1 timing. in this mode, the clock frequency is 1.544 mhz and the sync input is used to indicate active data timeslots. the clocks are gapped internally in the m28525/9 during inactive timeslots. atm cell bytes are continuously mapped into active timeslots. figure 1-31. cn8370 interface - e1 timing diagram lsb msb 2.048 mhz clock tx framer marker tx serial data ts0 ts31 0 255 t1 mod count lsb msb rx framer marker rx serial data ts0 ts31 0 255 t1 mod count general notes: in e1 mode, atm cells are mapped inot time slots 1-15 and 17-31 as described in recommendation g.804.
functional description 28529-dsh-001-k mindspeed technologies ? 98 mindspeed proprietary and confidential figure 1-33 shows an example of fractional e1 timing. in fr actional e1 mode, the clock frequency is 2.048 mhz, and the sync inputs are used to indicate active data timeslots. the clocks are gapped internally in the m28525/9 during inactive timeslots. atm cell bytes are continuously mapped into active timeslots. 1.14.2.5.3 dsl mode interface in dsl mode, the clock frequency can be up to 8.192 mhz. on the receive side, the sync input signals tell the tc port receiver to ignore the corresponding bits on the data bus. this can be used to mask out overhead bits. other than such overhead bits, the receive data stream should contain only serialized atm cells. on the transmit side, sync is an output and is used to indicate the start of cell ? the msb of the first byte of the cell. only serialized atm data cells are present in the transmit data stream the m2852x has a dsl mode in terface as illustrated in figure 1-34 . this mode allows connection with framers that require frame synchronization. the m2852x receives a data stream from the external framer, performs bit level cell figure 1-32. fractional t1 timing. figure 1-33. fractional e1 timing. note: to enable fractional t1/e1 on a link, the appropr iate enfrac bits must be set in the tc control registers, (tcctrl0-tc ctrl7). the phytype[2:0] bits in the port mode control register for the link should also be configur ed to be in xdsl framing mode (pmode[2:0] = 110). cgen[3] (dslsyncpol) must also be set to 1. ts24 f ts1 ts2 (inactive) ts3 ts24 ts2 ts3 sprxclk (1.544 mhz) sprxsync sprxdata sptxclk (1.544 mhz) sptxsync sptxdata ts31 ts0 (overhead) ts1 (inactive) ts2 ts3 ts31 ts1 ts3 sprxclk (2.048 mhz) sprxsync sprxdata sptxclk (2.048 mhz) sptxsync sptxdata
functional description 28529-dsh-001-k mindspeed technologies ? 99 mindspeed proprietary and confidential delineation, and passes the atm cells to the atm layer device. in this mode, the framer must ensure that only atm cells are present in the receive data stream. the m2852x performs the inverse process on transmitted data. 1.14.2.5.4 general purp ose mode interface the m2852x has a genera l purpose mode interf ace as illustrated in figure 1-35 . this mode allows connection with framers that do not provide frame synchronization. the m2852x receives a data stream from the external framer, performs bit level cell delineation, and passes the atm cells to the atm layer device. in this mode, the framer must ensure that only atm cells are present in the receive data stream. the m2852x performs the inverse process on transmitted data. figure 1-34. dsl mode general notes: 1. rxdata is ignored when sprxsync is asserted based on it's programmable active level. this may be used to mask overhead bits in the receive data stream. polarity is shown as active low in above figure. 2. txsync indicates the start of cell. 3. tx and rx are asynchronous. port x tx serial data tx clock sptxclk sprxclk sptxdata dsl modem rx serial data sprxdata txdata rxdata txclk m28529 bit clock tx serial data transparent cell transport msb rx serial data (1) 500027_014 sptxsync sprxsync sptxsync txsync sprxsync rx sync oh tx sync (1) rx clock rxclk
functional description 28529-dsh-001-k mindspeed technologies ? 100 mindspeed proprietary and confidential in general purpose framing mode, there is no frame synchronization or overhead bit indicators ? the sync inputs should be held high. the receive data streams should contain only serialized atm cells. the transmit data will only contained serialized atm cells. 1.14.2.5.5 interleaved highway interface the m2852x has inte rleaved highway interf aces (8-m28529, 4-m28 525) as illustrated in figure 1-36 and figure 1- 37 . four serial data streams can be combined together into one serial data stream using an interleaved highway interface. this interface is designed to communicate with mindspeed's cx2839x framer devices, running in internally multiplexed mode. figure 1-35. general purpose mode general notes: 1. in general purpose mode, the sptxsync and sprxsync pins must be held in the active state (active state depends on the sync polarity - txsyncpol and rxsyncpol bits are set in the iomode register). 2. diagram shows default values for txclkpol and rxclkpol (iomode register). 400 ? 1168k clock (1) tx serial data transparent cell transport msb rx serial data 500027_014a port x tx serial data clock sptxclk sprxclk sptxdata bt8970 rx serial data sprxdata tser rser bclk m28529 sptxsync sprxsync +3.3 v msb
functional description 28529-dsh-001-k mindspeed technologies ? 101 mindspeed proprietary and confidential figure 1-36. interfacing interleaved highway to cx2839x (frame sync provided by cx2389x) cx2839x m28529 rindo rfsync rpcmo rsbcki txindo tfsync tpcmi tsbcki ihrxindo ihrxsync ihrxdata ihrxclk ihtxindo ihtxsync ihtxdata ihtxclk 8.152 mhz receive clock 8.152 mhztransmit clock note: device configured for internally multiplexed mode
functional description 28529-dsh-001-k mindspeed technologies ? 102 mindspeed proprietary and confidential each interleaved highway interface carries four separate t1, e1, fractional t1, or fractional e1 style data streams (32 8-bit timeslots per frame). the data streams are interleaved one timeslot at a time. t1 links are supported over the interleaved highway interface, by mapping the 24 t1 timeslots (numbered 1-24) into the corresponding e1 timeslots. the remaining e1 timeslots, 0 and 25-31 are unused. the interleaved highway mode can be selected on a per group of four link basis where the groups are as follows: interleaved highway 0: serial streams 0-3 interleaved highway 1: serial streams 4-7 interleaved highway 2: serial streams 8-11 interleaved highway 3: serial streams 12-15 interleaved highway 4: serial streams 16-19 interleaved highway 5: serial streams 20-23 interleaved highway 6: serial streams 24-27 interleaved highway 7: serial streams 28-31 input pins ihrxsync and ihtxsync are provided to indicate the first bit (msb) of the first timeslot of the first data stream, in the receive and transmit directions respectively. the streams are multiplexed in order of the lowest numbered stream to highest number. figure 1-37. interfacing interleaved highway to cx2839x (frame sync externally provided) cx2839x m28529 rindo rfsync rpcmo rsbcki txindo tfsync tpcmi tsbcki ihrxindo ihrxsync ihrxdata ihrxclk ihtxindo ihtxsync ihtxdata ihtxclk 8.152 mhz receive clock 8.152 mhz transmit clock receive frame sync transmit frame sync note: device configured for internally multiplexed mode
functional description 28529-dsh-001-k mindspeed technologies ? 103 mindspeed proprietary and confidential fractional t1/e1 is also supported over the interleaved highway interface. two extra signals, ihrxindo and ihtxindo, are used to indicate which timeslots are active on each of the data streams. these signals should be high for active timeslots. active timeslots in each case are as follows (timeslot 0 is always inactive as it is used for overhead in e1 frames, and has no corresponding timeslot in t1 frames): full t1: timeslots 1-24 are used. full e1: timeslots 1-15 and 17-31 are used. fractional t1: subset of timeslots 1-24 is used. fractional e1: subset of timeslots 1-15 and 17-31 are used. the fractional t1/e1 logic is automatically enabled when using the interleaved highway interface, to provide the necessary internal clock gating. figure 1-38 shows how the datastreams are combined on the interleave highway. in this example time slots 31a and ts0b are inactive as indicated by ihrxindo being low. if for example figure 1- 38 represented interleaved highway 5, the streams would be grouped as follows: a = stream 20, b = stream 21, c = stream 22, d = stream 23. figure 1-38. combined datastreams on the interleaved highway figure 1-39. full t1 interleaved highway frame ts31a ihrxcl k ihrxdata i hrxsync i hrxindo ts31b ts31c ts31d ts0a ts0b ts0c ts0d 0 a ihrxdata (continued) ihrxindo ihrxsync ihrxdata ihrxindo (continued) ihrxsync (continued) 0 b 0 c 0 d 1 a 1 b 1 c 1 d 2 a 2 b 2 c 2 d 3 a 3 b 3 c 3 d 4 a 4 b 4 c 4 d 5 a 5 b 5 c 5 d 6 a 6 b 6 c 6 d 7 a 7 b 7 c 7 d 8 a 8 b 8 c 8 d 9 a 9 b 9 c 9 d 10 a 10 b 10 c 10 d 11 a 11 b 11 c 11 d 12 a 12 b 12 c 12 d 13 a 13 b 13 c 13 d 14 a 14 b 14 c 14 d 15 a 15 b 15 c 15 d 16 a 16 b 16 c 16 d 17 a 17 b 17 c 17 d 18 a 18 b 18 c 18 d 19 a 19 b 19 c 19 d 20 a 20 b 20 c 20 d 21 a 21 b 21 c 21 d 22 a 22 b 22 c 22 d 23 a 23 b 23 c 23 d 24 a 24 b 24 c 24 d 25 a 25 b 25 c 25 d 26 a 26 b 26 c 26 d 27 a 27 b 27 c 27 d 28 a 28 b 28 c 28 d 29 a 29 b 29 c 29 d 30 a 30 b 30 c 31 a 30 a 31 b 31 c 31 d note: only the transmt frame structure is shown, but the receive frame structure is identical
functional description 28529-dsh-001-k mindspeed technologies ? 104 mindspeed proprietary and confidential figure 1-41 is a block diagram showing how four serial links are combined. figure 1-40. full e1 interleaved highway frame note: the tc processors belonging to the interleaved highway group should be configured in xdsl mode, by setting phytype to 110 in the port mode control registers (pmode[2:0]) 0x04, as this is required when using the fractional t1/e1 logic. also, the iomode registers 0x05 should be set to their default values. thi s is because the clock polarities in interleaved highway mode are controlled via the tcctrl registers. also the internal sync inputs to the tc processor are tied low (inactive state when iomode[6] and iomode[4] are set to default values in xdsl mode) so that they have no effect note: the t1/e1 streams must be locked to the 8.192 mhz clock rate. 0 a ihrxindo ihrxsync ihrxdata 0 b 0 c 0 d 1 a 1 b 1 c 1 d 2 a 2 b 2 c 2 d 3 a 3 b 3 c 3 d 4 a 4 b 4 c 4 d 5 a 5 b 5 c 5 d 6 a 6 b 6 c 6 d 7 a 7 b 7 c 7 d 8 a 8 b 8 c 8 d 9 a 9 b 9 c 9 d 10 a 10 b 10 c 10 d 11 a 11 b 11 c 11 d 12 a 12 b 12 c 12 d 13 a 13 b 13 c 13 d 14 a 14 b 14 c 14 d 15 a 15 b 15 c 15 d 16 a 16 b 16 c 16 d 17 a 17 b 17 c 17 d 18 a 18 b 18 c 18 d 19 a 19 b 19 c 19 d 20 a 20 b 20 c 20 d 21 a 21 b 21 c 21 d 22 a 22 b 22 c 22 d 23 a 23 b 23 c 23 d 24 a 24 b 24 c 24 d 25 a 25 b 25 c 25 d 26 a 26 b 26 c 26 d 27 a 27 b 27 c 27 d 28 a 28 b 28 c 28 d 29 a 29 b 29 c 29 d 30 a 30 b 30 c 31 a 30 a 31 b 31 c 31 d ihrxsync (continued) ihrxindo (continued) ihrxdata (continued) note: only the transmt frame structure is shown, but the receive frame structure is identical
functional description 28529-dsh-001-k mindspeed technologies ? 105 mindspeed proprietary and confidential 1.15 general issues 1.15.1 micro interface the microprocessor interface transfers control and status information in 8-bit data transfers between the external microprocessor and m2852x by means of write and/or read ac cess to internal registers. this interface allows the microprocessor to configure the m2852x by writing various control registers. these control registers can also be read for configuration confirmation. this interface also prov ides the ability to read the de vice?s current condition via its status registers and counters. summary status is available for rapid interrupt identification. the microprocessor interface can operate in either an asynchronous mode or a synchronous mode. the msyncmode (pin ae24) determines which mode is active. in the synchronous mode, the timing of these signals is sync hronized to microclk , which is intended to be directly driven by the external microprocessor. 1.15.1.1 resets there are four software controlled reset functions, two at the device level and two at the port level. the two levels allow a user to reset either the entire m2852x with one command or only a port within the device. the two logic resets allow the user to keep the device or port in a reset state while the control registers are being programmed. when the reset bit is deasserted, all changes to the registers take place simultaneously. figure 1-41. interleaved highway mux note: the microclk is required for both modes. in asynchronous mode, a microclk frequency of up to 66mhz, must be present but can be asynchronous to the other microprocessor signals. in synchronous mode, microclk is limited to 25mhz. line interface n interleaved highway group tc cell processor line interface n+1 tc cell processor line interface n+2 tc cell processor line interface n+3 4 x 1 mux tc cell processor
functional description 28529-dsh-001-k mindspeed technologies ? 106 mindspeed proprietary and confidential at the device level, the software-controlled devmstrst, bit 7, in the genctrl register (0x0f00), restarts all device functions and sets the control and status registers, including ima, to their default values except this bit (devmstrst). the devlgcrst, bit 6, in the genctrl register (0x0f00) restarts all device functions in the tc block but leaves all control registers unaffected. during a device logic reset the ima core is held in a complete reset state. at the port level, the prtmstrst, bit 7, in the pmode register (0x04), restarts all port functions and sets the registers for the associated port to their default values ex cept this bit (prtmstrst). the prtlgcrst, bit 6, in the pmode register (0x04) restarts all functions but leaves the port control registers unaffected. 1.15.1.2 counters (tc block only) the m2852x counters record events within the tc block. two types of events are recorded: error events, such as section bip errors, and transmission events, such as transmitted atm cells. counters comprised of more than one register must be accessed by reading the least significant byte (lsb) first. this guarantees that the value contained in each component register accurately reflects the composite counter value at the time the lsb was read, because the counter may be updated while the component registers are being read. each counter is large enough to accommodate the maximum number of events that may occur within a one-second interval. the counters are cleared after being read. therefore, if the counters are read every second, the application will receive an accu rate recording of all events. 1.15.1.2.1 one-second latching the m2852x?s implementation of one-second latching ensures the integrity of the statistics being gathered by the network management software. internal statistics counters can be latched at one-second intervals, which are synchronized to the onesecio pin (pin ae26). therefore, the data read from the statistic counters represents the same one second of real-time data, independent of network management software timing. the m2852x implements one-second latching for both status signals and counter values. when the enstatlat (bit 5) in the genctrl register (0xf00) is written to a logical 1, a read from any of the status registers returns the state of the device at the time of the previous onesecio (pin ae26) assertion. when the encntrlat (bit 4) in the genctrl register (0xf00) is written to a logical 1, a read from any of the counters returns the state of the device at the time of the previous onesecio (pin ae26) assertion. every second, the counter is read, moved to the latch, and the counter is cleared. the latch is cleared when read. software can configure the onesecio pin as an output that equals the input from the 8khzin divided by 8000. when configured as an input, status registers and counters may be latched on the rising edge of this input. see bit 0 of the genctrl register (0xf00). note: if configuring the device for pass-through operation, a minimum delay of 25 us for ima_sysclk of 66 mhz or 33 us for ima_sysclk of 50 mhz is required from the release of device reset (devmstrst) to the first access of the ima_rx_trans_table register or ima_rx_atm_trans_table register (0x818/0x819). note: when latching is disabled and a counter is wider than one byte, the lsb should be read first to retain the values of the other bytes for a subsequent read.
functional description 28529-dsh-001-k mindspeed technologies ? 107 mindspeed proprietary and confidential 1.15.1.2.2 interrupts the m2852x?s interrupt indications can be classified as either single- or dual-event; a single-event interrupt is triggered by a status assertion; a dual-event interrupt is triggered by either a status assertion or deassertion. both types of interrupts are further described in the following examples. single-event interrupt: when a parity error occurs on the utopia transmit data bus, an interrupt is generated on parerrint, bit 7, in the txcellint register (0x2c). this bit is cleared when read. dual-event interrupt: when locd occurs, bit 7 of the corresponding rxcellint register (0x0d) is set to 1. this bit is cleared when the register is read. once cell delinea tion is recovered, bit 7 is set to 1 again, generating another interrupt. all interrupt bits have a corresponding enable bit. this a llows software to disable or mask interrupts as required. the m2852x uses three levels of interrupt indications. the first level consists of receive or transmit interrupt indications, which correspond to specific events on a specific port. the second level summarizes first level interrupts and indicates framer and one-second interrupts for each port. the third level indicates which port generated an interrupt. the first level interrupt indications are located in registers txcellint and rxcellint for each port. each interrupt bit in these registers can be disabled in the corresponding encellr or encellt register, respectively. the result is then ored into the appropriate bit in the port?s sumint register. the second level consists of summary interrupt indications, located in the sumint register. it also includes the onesecint and the exint indications. each interrupt bit in these registers can be disabled in the corresponding ensumint register. the result is then ored into the appropriate bit in the sumport register. the third level contains the overall interrupt indications for each port in the sumport register. these bits can be disabled in the ensumport register. the result is ored to the microint* pin. the microint* pin can be enabled or disabled by setting the enintpin (bit 3) in the genctrl register (0x0f00). figure 1-42 illustrates the flow chart of the interrupt generation process and figure 1-43 illustrates th e registers involved in the interrupt generation process. note: the ima block does not generate interrupts.
functional description 28529-dsh-001-k mindspeed technologies ? 108 mindspeed proprietary and confidential figure 1-42. interrupt indication flow chart txcellint or rxcellint event occurs sumint interrupt indication enabled ? individual interrupt indication enabled ? no ye s ye s no return sumport port indication enabled ? interrupt pin (mint*) enabled ? set sumint interrupt indication bit set sumport interrupt indication bit onesecint or exint event occurs set individual interrupt indication bit set interrupt pin (mint*) no no ye s ye s 500027_015
functional description 28529-dsh-001-k mindspeed technologies ? 109 mindspeed proprietary and confidential figure 1-43. interrupt indication diagram (tc block) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 onesecint portint24 portint31 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 rxcellint txcellint resvd resvd resvd resvd resvd resvd parerrint socerrint txovflint rxovflint cellsentint resvd resvd resvd locdint hecdetint heccorrint cellrcvint idlercvint nonmatchint nonzergfcint resvd 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 rxcellint txcellint resvd resvd resvd resvd resvd resvd parerrint socerrint txovflint rxovflint cellsentint resvd resvd resvd locdint hecdetint heccorrint cellrcvint idlercvint nonmatchint nonzergfcint resvd microint input to latch enabled by ensumint sumint (0x1c0) sumint (0x000) input to latch enabled by ensumint input to latch enabled by enonesecint (0xf19) input to latch enabled by ensumport0 (0xf06) input to latch enabled by ensumport3 (0xf0c) sumport0 (0xf05) sumport3 (0xf0b) txcellint (0x1ec) txcellint (0x02c) rxcellint (0x1ed) rxcellint (0x02d) ... . . .
functional description 28529-dsh-001-k mindspeed technologies ? 110 mindspeed proprietary and confidential 1.15.1.2.3 interrupt servicing when an interrupt occurs on the microint* pin (pin aa1), it could have been generated by any of 385 events. the m2852x?s interrupt indication structure ensures that no more than a maximum of seven register reads are needed to determine the source of an interrupt. the interrupt is traced back to its source using the following steps: 1. read the sumport0-3 registers and the onesecint register to see which port(s) shows an interrupt and/or whether there was a one second interrupt. 2. read the appropriate sumint register to see which bit(s) shows an interrupt. bit 0, rxcellint, reflects acti vity in the rxcellint register. bit 1, txcellint, reflects activity in the txcellint register. bits 2?7 are reserved. 3. if necessary, read the appropriate txcellint or rxcellint register. all level 1 bits are cleared when the register is read. once the register is read, all bits in that register are reset to their default values. therefore, interrupt service routines must be designed to handle multiple interrupts in the same registers. in level 2, onesecint and exint are cleared when the register is read. however, the txcellint and rxcellint bits are cleared only when the corresponding level 1 register is read and cleared. level 3 bits are cleared when the entire corresponding level 2 register has been read and cleared.
28529-dsh-001-k mindspeed technologies ? 111 mindspeed proprietary and confidential 2.0 registers 2.1 address map the m2852x registers control and observe the device?s operations. ta bl e 2-1 lists the address ranges that represent a device control and status range. the registers in each port range are replicated for the other ports. ta bl e 2-2 lists the device-level control and status registers. ta bl e 2-3 lists the port-level control and status registers. all registers are 8 bits wide. all control registers can be read to verify contents. note: control bits that do not have a documented f unction are reserved and must be written to a logical 0. table 2-1. address ranges (1 of 2) port offset address range (hex) description port base address (hex) 0000?003f port 0 control and status registers 0000 0040?007f port 1 control and status registers 0040 0080?00bf port 2 control and status registers 0080 00c0?00ff port 3 control and status registers 00c0 0100?013f port 4 control and status registers 0100 0140?017f port 5 control and status registers 0140 0180?01bf port 6 control and status registers 0180 01c0?01ff port 7 control and status registers 01c0 0200-023f port 8 control and status registers 0200 0240-027f port 9 control and status registers 0240 0280-02bf port 10 control and status registers 0280 02c0-02ff port 11 control and status registers 02c0 0300-033f port 12 control and status registers 0300 0340-037f port 13 control and status registers 0340 0380-03bf port 14 control and status registers 0380 03c0-03ff port 15 control and status registers 03c0 0400-043f port 16 control and status registers 0400 0440-047f port 17 control and status registers 0440 0480-04bf port 18 control and status registers 0480
registers 28529-dsh-001-k mindspeed technologies ? 112 mindspeed proprietary and confidential the device level registers in ta b l e 2-2 provide control for the device?s major operating modes, as well as status and control for summary interrupts. 04c0-04ff port 19 control and status registers 04c0 0500-053f port 20 control and status registers 0500 0540-057f port 21 control and status registers 0540 0580-05bf port 22 control and status registers 0580 05c0-05ff port 23 control and status registers 05c0 0600-063f port 24 control and status registers 0600 0640-067f port 25 control and status registers 0640 0680-06bf port 26 control and status registers 0680 06c0-06ff port 27 control and status registers 06c0 0700-073f port 28 control and status registers 0700 0740-077f port 29 control and status registers 0740 0780-07bf port 30 control and status registers 0780 07c0-07ff port 31 control and status registers 07c0 0800-0eff ima control and status registers ? 0f00-0fff device control and status registers ? table 2-2. device control and status registers (1 of 2) address name type onesec latching description page number 0x0f00 genctrl r/w ? general device cont rol register page 179 0x0f01 partnum r/w ? part and version number page 179 0x0f02 phyintfc r/w ? phy-side interface control register page 180 0x0f03 atmintfc r/w ? atm-side interface control register page 180 0x0f04 statout r ? output st atus control register page 180 0x0f05 sumport0 r/w ? summary interrupt status register (tc ports 0-7) page 181 0x0f06 ensumport0 r ? summary interrupt control register (tc ports 0-7) page 181 0x0f07 sumport1 r/w ? summary interrupt status register (tc ports 8-15) page 182 0x0f08 ensumport1 r ? summary interrupt control register (tc ports 8-15) page 182 0x0f09 sumport2 r/w ? summary interrupt status register (tc ports 16-23) page 183 0x0f0a ensumport2 r ? summary interrupt control register (tc ports 16-23) page 183 0x0f0b sumport3 r/w ? summary interrupt status register (tc ports 24-31) page 184 0x0f0c ensumport3 r ? summary interrupt control register (tc ports 24-31) page 184 0x0f0d ? ? reserved, set register to all 0?s table 2-1. address ranges (2 of 2) port offset address range (hex) description port base address (hex)
registers 28529-dsh-001-k mindspeed technologies ? 113 mindspeed proprietary and confidential the registers listed in ta bl e 2-3 are replicated for each port. two methods can be used to determine the exact address of a specific register in a specific port. all numbers are in hexadecimal. 1. add the port offset address to the port base address as shown in table 2-1 . for example: for port 3, iomode register 0xc0 (port 3 base address) + 0x05 (port offset address) = 0xc5 2. use the following formula: 0x40 (port register map size) n (port number) + port offset address = exact register address 0x0f0e ? ? reserved, set register to all 0?s 0x0f0f scratch ? scratch pad register page 184 0x0f10 tcctrl0 ? tc control register for tc ports 0-3 page 185 0x0f11 tcctrl1 ? tc control register for tc ports 4-7 page 185 0x0f12 tcctrl2 ? tc control register for tc ports 8-11 page 186 0x0f13 tcctrl3 ? tc control register for tc ports 12-15 page 186 0x0f14 tcctrl4 ? tc control register for tc ports 16-19 page 187 0x0f15 tcctrl5 ? tc control register for tc ports 20-23 page 187 0x0f16 tcctrl6 ? tc control register for tc ports 24-27 page 188 0x0f17 tcctrl7 ? tc control register for tc ports 28-31 page 188 0x0f18 onesecint ? one second interrupt status register page 188 0x0f19 enonesecint ? one second interrupt control register page 189 table 2-3. port control and status registers (1 of 3) port offset address name type one-second latching description page number 0x00 sumint r ? summary interrupt indication st atus register page 150 0x01 ensumint r/w ? summary interrupt control register page 151 0x02 ? ? ? reserved, set to a logical 0 ? 0x03 ? ? ? reserved, set to a logical 0 ? 0x04 pmode r/w ? port mode control register page 152 0x05 iomode r/w ? input/output mode control register page 153 0x08 cgen r/w ? cell generation control register page 154 0x09 hdrfield r/w ? header field control register page 155 0x0a idlpay r/w ? transmit idle cell payload control register page 155 0x0b errpat r/w ? error pattern control register page 156 0x0c cval r/w ? cell validation control register page 156 0x0d utop1 r/w ? utopia control register 1 page 157 0x0e utop2 r/w ? utopia control register 2 page 157 table 2-2. device control and status registers (2 of 2) address name type onesec latching description page number
registers 28529-dsh-001-k mindspeed technologies ? 114 mindspeed proprietary and confidential 0x0f udf2 r/w ? udf2 control register page 158 0x10 txhdr1 r/w ? transmit cell header control register 1 page 158 0x11 txhdr2 r/w ? transmit cell header control register 2 page 159 0x12 txhdr3 r/w ? transmit cell header control register 3 page 159 0x13 txhdr4 r/w ? transmit cell header control register 4 page 160 0x14 txidl1 r/w ? transmit idle cell header control register 1 page 160 0x15 txidl2 r/w ? transmit idle cell header control register 2 page 161 0x16 txidl3 r/w ? transmit idle cell header control register 3 page 161 0x17 txidl4 r/w ? transmit idle cell header control register 4 page 162 0x18 rxhdr1 r/w ? receive cell header control register 1 page 162 0x19 rxhdr2 r/w ? receive cell header control register 2 page 163 0x1a rxhdr3 r/w ? receive cell header control register 3 page 163 0x1b rxhdr4 r/w ? receive cell header control register 4 page 164 0x1c rxmsk1 r/w ? receive cell mask control register 1 page 164 0x1d rxmsk2 r/w ? receive cell mask control register 2 page 165 0x1e rxmsk3 r/w ? receive cell mask control register 3 page 165 0x1f rxmsk4 r/w ? receive cell mask control register 4 page 166 0x20 rxidl1 r/w ? receive idle cell header control register 1 page 166 0x21 rxidl2 r/w ? receive idle cell header control register 2 page 167 0x22 rxidl3 r/w ? receive idle cell header control register 3 page 167 0x23 rxidl4 r/w ? receive idle cell header control register 4 page 168 0x24 idlmsk1 r/w ? receive idle ce ll mask control register 1 page 168 0x25 idlmsk2 r/w ? receive idle ce ll mask control register 2 page 169 0x26 idlmsk3 r/w ? receive idle ce ll mask control register 3 page 169 0x27 idlmsk4 r/w ? receive idle ce ll mask control register 4 page 170 0x28 encellt r/w ? transmit cell interrupt control register page 170 0x29 encellr r/w ? receive cell interrupt control register page 171 0x2a ? ? ? reserved, set to a logical 0 ? 0x2b ? ? ? reserved, set to a logical 0 ? 0x2c txcellint r ? transmit cell interrupt indication control register page 171 0x2d rxcellint r ? receive cell interr upt indication control register page 172 0x2e txcell r (1) transmit cell status control register page 172 0x2f rxcell r (1) receive cell status control register page 173 0x30 idlcntl r (2) idle cell receive counter (low byte) page 173 0x31 idlcnth r (2) idle cell receive counter (high byte) page 174 table 2-3. port control and status registers (2 of 3) port offset address name type one-second latching description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 115 mindspeed proprietary and confidential ta bl e 2-4 lists the control registers used for transmission of traffic. ta bl e 2-5 lists the control registers used for reception of traffic. 0x33 locdcnt r (2) locd event counter page 174 0x34 txcntl r (2) transmitted cell counter (low byte) page 175 0x35 txcnth r (2) transmitted cell counter (high byte) page 175 0x37 corrcnt r (2) corrected hec error counter page 176 0x38 rxcntl r (2) received cell counter (low byte) page 176 0x39 rxcnth r (2) received cell counter (high byte) page 177 0x3b unccnt r (2) uncorrected hec error counter page 177 0x3c noncntl r (2) non-matching cell counter (low byte) page 178 0x3d noncnth r (2) non-matching cell counter (high byte) page 178 0x3e ? ? ? reserved, set to a logical 0 ? 0x3f ? ? ? reserved, set to a logical 0 ? footnote: (1) one-second latching is enabled by se tting enstatlat (bit 5) in the genc trl register (0xf00) to a logical 1. (2) one-second latching is enabled by setting encntrlat (bit 4) in the mode register (0xf00) to a logical 1. table 2-4. cell transmit registers port offset address name description page number 0x08 cgen cell generation control register page 154 0x09 hdrfield header field control register page 155 0x0a idlpay transmit idle cell payload control register page 155 0x0b errpat error pattern control register page 156 0x10 txhdr1 transmit cell header control register 1 page 158 0x11 txhdr2 transmit cell header control register 2 page 159 0x12 txhdr3 transmit cell header control register 3 page 159 0x13 txhdr4 transmit cell header control register 4 page 160 0x14 txidl1 transmit idle cell header control register 1 page 160 0x15 txidl2 transmit idle cell header control register 2 page 161 0x16 txidl3 transmit idle cell header control register 3 page 161 0x17 txidl4 transmit idle cell header control register 4 page 162 table 2-3. port control and status registers (3 of 3) port offset address name type one-second latching description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 116 mindspeed proprietary and confidential ta bl e 2-6 lists the control registers for the utopia operations. table 2-5. cell receive registers port offset address name description page number 0x0c cval cell validation control register page 156 0x18 rxhdr1 receive cell head er control register 1 page 162 0x19 rxhdr2 receive cell head er control register 2 page 163 0x1a rxhdr3 receive cell head er control register 3 page 163 0x1b rxhdr4 receive cell head er control register 4 page 164 0x1c rxmsk1 receive cell ma sk control register 1 page 164 0x1d rxmsk2 receive cell ma sk control register 2 page 165 0x1e rxmsk3 receive cell ma sk control register 3 page 165 0x1f rxmsk4 receive cell ma sk control register 4 page 166 0x20 rxidl1 receive idle cell header control register 1 page 166 0x21 rxidl2 receive idle cell header control register 2 page 167 0x22 rxidl3 receive idle cell header control register 3 page 167 0x23 rxidl4 receive idle cell header control register 4 page 168 0x24 idlmsk1 receive idle cell mask control register 1 page 168 0x25 idlmsk2 receive idle cell mask control register 2 page 169 0x26 idlmsk3 receive idle cell mask control register 3 page 169 0x27 idlmsk4 receive idle cell mask control register 4 page 170 table 2-6. utopia registers port offset address name description page number 0x0d utop1 utopia control register 1 page 157 0x0e utop2 utopia control register 2 page 157
registers 28529-dsh-001-k mindspeed technologies ? 117 mindspeed proprietary and confidential ta bl e 2-7 and ta b l e 2-8 list interrupt enables, interrupt indications, and status information. table 2-7. status and interrupt registers port address name description page number 0xf05 sumport0 summary port in terrupt status register 0 page 181 0xf06 ensumport0 summary port interrupt control register 0 page 181 0xf07 sumport1 summary port in terrupt status register 1 page 182 0xf08 ensumport1 summary port interrupt control register 1 page 182 0xf09 sumport2 summary port in terrupt status register 2 page 183 0xf0a ensumport2 summary port interrupt control register 2 page 183 0xf0b sumport3 summary port in terrupt status register 3 page 184 0xf0c ensumport3 summary port interrupt control register 3 page 184 table 2-8. status and interrupt registers (offset registers) port offset address name description page number 0x00 sumint summary interrupt indication status register page 150 0x01 ensumint summary interrupt control register page 151 0x28 encellt transmit cell interrupt control register page 170 0x29 encellr receive cell interrupt control register) page 171 0x2c txcellint transmit cell inte rrupt indication status register page 171 0x2d rxcellint receive cell interr upt indication status register page 172 0x2e txcell transmit cell status register page 172 0x2f rxcell receive ce ll status register page 173
registers 28529-dsh-001-k mindspeed technologies ? 118 mindspeed proprietary and confidential ta bl e 2-9 lists the m2852x?s counters. when the counters fill, they saturate and do not roll over. the counts have been sized to ensure against saturation within a one-sec ond interval. therefore, when one-second latching is enabled, the counters are read and cleared before they can saturate. all counters are cleared when read. ta bl e 2-10 lists ima control an d status information. table 2-9. counters port offset address name description page number 0x30 idlcntl idle cell receive counter [low byte] page 173 0x31 idlcnth idle cell receive counter [high byte] page 174 0x33 locdcnt locd event counter page 174 0x34 txcntl transmitted cell counter [low byte] page 175 0x35 txcnth transmitted cell counter [high byte] page 175 0x37 corrcnt corrected hec error counter page 176 0x38 rxcntl received cell counter [low byte] page 176 0x39 rxcnth received cell counter [high byte] page 177 0x3b unccnt uncorrected hec error counter page 177 0x3c noncntl non-matching ce ll counter [low byte] page 178 0x3d noncnth non-matching cell counter [high byte] page 178 table 2-10. ima control and status registers (1 of 33) address name description page number 0x800 ima_ver_1_config device version i page 189 0x801 ima_ver_2_config device version ii page 189 0x802 ima_subsys_config configuration control page 190 0x803 ima_misc_status miscellaneous status page 190 0x804 ima_misc_config miscellaneous control page 191 0x805 ima_mem_low_test memory test address page 191 0x806 ima_mem_hi_test memory test address page 192 0x807 ima_mem_test_ctl memory test control page 192 0x808 ima_mem_test_data memory test data page 192 0x809 ima_lnk_diag_ctl link diagnostic control page 192 0x80a ima_lnk_diff_del link differential delay page 192 0x80b ima_rcv_lnk_anomalies receive link anomalies page 193 0x80c ima_phy_loopback ima phy side utopia loopback page 194 0x80e ima_diag_xor_bit address diagnostic page 194 0x80f ima_diag diagnostic register page 194 0x810 ima_tim_ref_mux_ctl_addr trl control address page 195
registers 28529-dsh-001-k mindspeed technologies ? 119 mindspeed proprietary and confidential 0x811 ima_tim_ref_mux_ctl_data trl control data page 196 0x812 ima_rx_persist_config receive persistence page 197 0x813 ima_atm_utopia_bus_ctl atm utopia control page 197 0x814 ima_diff_delay_addr diff. delay control address page 198 0x815 ima_diff_delay_data diff. delay control data page 198 0x816 ima_dsl_clock_gen_addr dsl clock generator control address page 199 0x817 ima_dsl_clock_gen_data dsl clock generator control data page 200 0x818 ima_rx_trans_table recei ve translation table address page 201 0x819 ima_rx_atm_trans_table receive tr anslation table internal channel page 202 0x81b ima_tx_trans_table transmit translation table address page 203 0x81c ima_tx_atm_trans_table transmit translation table internal channel page 203 0x81e ima_lnk_sem link table control page 230 0x81f ima_grp_1to4_sem groups 1?4 table control page 204 0x91f ima_grp_5to8_sem groups 5?8 table control page 204 0xa1f ima_grp_9to12_sem groups 9?12 table control page 205 0xb1f ima_grp_13to16_sem groups 13?16 table control page 206 0xc1f ima_grp_17to20_sem groups 17?20 table control page 206 0xc9f ima_grp_21to24_sem groups 21?24 table control page 207 0xd1f ima_grp_25to28_sem groups 25?28 table control page 207 0xd9f ima_grp_29to32_sem groups 29?32 table control page 208 transmit groups 1?4 configuration tables 0x820 ima_tx_grp1_rx_test_pattern tx grp 1 rx test pattern page 208 0x821 ima_tx_grp1_ctl tx grp 1 control page 209 0x822 ima_tx_grp1_first_phy_addr tx grp 1 first link address page 210 0x823 ima_tx_grp1_id tx grp 1 tx group id page 211 0x824 ima_tx_grp1_stat_ctl tx grp 1 status / control page 212 0x825 ima_tx_grp1_timing_inf o tx grp 1 timing control page 213 0x826 ima_tx_grp1_test_ctl tx grp 1 test control page 214 0x827 ima_tx_grp1_tx_test_pattern tx grp 1 tx test pattern page 215 0x828 ima_tx_grp2_rx_test_pattern tx grp 2 rx test pattern page 208 0x829 ima_tx_grp2_ctl tx grp 2 control page 209 0x82a ima_tx_grp2_first_phy_addr tx grp 2 first link address page 210 0x82b ima_tx_grp2_id tx grp 2 tx group id page 211 0x82c ima_tx_grp2_stat_ctl tx grp 2 status / control page 212 0x82d ima_tx_grp2_timing_inf o tx grp 2 timing control page 213 table 2-10. ima control and status registers (2 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 120 mindspeed proprietary and confidential 0x82e ima_tx_grp2_test_ctl tx grp 2 test control page 214 0x82f ima_tx_grp2_tx_test_pattern tx grp 2 tx test pattern page 215 0x830 ima_tx_grp3_rx_test_pattern tx grp 3 rx test pattern page 208 0x831 ima_tx_grp3_ctl tx grp 3 control page 209 0x832 ima_tx_grp3_first_phy_addr tx grp 3 first link address page 210 0x833 ima_tx_grp3_id tx grp 3 tx group id page 211 0x834 ima_tx_grp3_stat_ctl tx grp 3 status / control page 212 0x835 ima_tx_grp3_timing_inf o tx grp 3 timing control page 213 0x836 ima_tx_grp3_test_ctl tx grp 3 test control page 214 0x837 ima_tx_grp3_tx_test_pattern tx grp 3 tx test pattern page 215 0x838 ima_tx_grp4_rx_test_pattern tx grp 4 rx test pattern page 208 0x839 ima_tx_grp4_ctl tx grp 4 control page 209 0x83a ima_tx_grp4_first_phy_addr tx grp 4 first link address page 210 0x83b ima_tx_grp4_id tx grp 4 tx group id page 211 0x83c ima_tx_grp4_stat_ctl tx grp 4 status / control page 212 0x83d ima_tx_grp4_timing_inf o tx grp 4 timing control page 213 0x83e ima_tx_grp4_test_ctl tx grp 4 test control page 214 0x83f ima_tx_grp4_tx_test_pattern tx grp 4 tx test pattern page 215 tx utopia addresses 0 - 3 cell counters 0x840 0x841 0x842 0x843 0x844 0x845 0x846 0x847 ima_tx_atm0_cell_count_lsb ima_tx_atm0_cell_count_msb ima_tx_atm1_cell_count_lsb ima_tx_atm1_cell_count_msb ima_tx_atm2_cell_count_lsb ima_tx_atm2_cell_count_msb ima_tx_atm3_cell_count_lsb ima_tx_atm3_cell_count_msb transmit utopia address 0x00 cell count lsbs transmit utopia address 0x00 cell count msbs transmit utopia address 0x01 cell count lsbs transmit utopia address 0x01 cell count msbs transmit utopia address 0x02 cell count lsbs transmit utopia address 0x02 cell count msbs transmit utopia address 0x03 cell count lsbs transmit utopia address 0x03 cell count msbs page 216 rx utopia addresses 0 - 3 cell counters 0x850 0x851 0x852 0x853 0x854 0x855 0x856 0x857 ima_rx_atm0_cell_count_lsb ima_rx_atm0_cell_count_msb ima_rx_atm1_cell_count_lsb ima_rx_atm1_cell_count_msb ima_rx_atm2_cell_count_lsb ima_rx_atm2_cell_count_msb ima_rx_atm3_cell_count_lsb ima_rx_atm3_cell_count_msb receive utopia address 0x00 cell count lsbs receive utopia address 0x00 cell count msbs receive utopia address 0x01 cell count lsbs receive utopia address 0x01 cell count msbs receive utopia address 0x02 cell count lsbs receive utopia address 0x02 cell count msbs receive utopia address 0x03 cell count lsbs receive utopia address 0x03 cell count msbs page 218 table 2-10. ima control and status registers (3 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 121 mindspeed proprietary and confidential port 0?7 control and status 0x860 0x861 0x862 0x863 0x864 0x865 0x866 0x867 ima_tx_lnk0_ctl ima_tx_lnk1_ctl ima_tx_lnk2_ctl ima_tx_lnk3_ctl ima_tx_lnk4_ctl ima_tx_lnk5_ctl ima_tx_lnk6_ctl ima_tx_lnk7_ctl tx link 0 control tx link 1 control tx link 2 control tx link 3 control tx link 4 control tx link 5 control tx link 6 control tx link 7 control page 232 0x868 0x869 0x86a 0x86b 0x86c 0x86d 0x86e 0x86f ima_tx_lnk0_state ima_tx_lnk1_state ima_tx_lnk2_state ima_tx_lnk3_state ima_tx_lnk4_state ima_tx_lnk5_state ima_tx_lnk6_state ima_tx_lnk7_state tx link 0 status tx link 1 status tx link 2 status tx link 3 status tx link 4 status tx link 5 status tx link 6 status tx link 7 status page 233 0x870 0x871 0x872 0x873 0x874 0x875 0x876 0x877 ima_tx_lnk0_id ima_tx_lnk1_id ima_tx_lnk2_id ima_tx_lnk3_id ima_tx_lnk4_id ima_tx_lnk5_id ima_tx_lnk6_id ima_tx_lnk7_id tx link 0 assigned lid tx link 1 assigned lid tx link 2 assigned lid tx link 3 assigned lid tx link 4 assigned lid tx link 5 assigned lid tx link 6 assigned lid tx link 7 assigned lid page 234 0x880 0x881 0x882 0x883 0x884 0x885 0x886 0x887 ima_rx_lnk0_ctl ima_rx_lnk1_ctl ima_rx_lnk2_ctl ima_rx_lnk3_ctl ima_rx_lnk4_ctl ima_rx_lnk5_ctl ima_rx_lnk6_ctl ima_rx_lnk7_ctl rx link 0 control rx link 1 control rx link 2 control rx link 3 control rx link 4 control rx link 5 control rx link 6 control rx link 7 control page 235 0x888 0x889 0x88a 0x88b 0x88c 0x88d 0x88e 0x88f ima_rx_lnk0_state ima_rx_lnk1_state ima_rx_lnk2_state ima_rx_lnk3_state ima_rx_lnk4_state ima_rx_lnk5_state ima_rx_lnk6_state ima_rx_lnk7_state rx link 0 status rx link 1 status rx link 2 status rx link 3 status rx link 4 status rx link 5 status rx link 6 status rx link 7 status page 236 table 2-10. ima control and status registers (4 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 122 mindspeed proprietary and confidential 0x890 0x891 0x892 0x893 0x894 0x895 0x896 0x897 ima_rx_lnk0_defect ima_rx_lnk1_defect ima_rx_lnk2_defect ima_rx_lnk3_defect ima_rx_lnk4_defect ima_rx_lnk5_defect ima_rx_lnk6_defect ima_rx_lnk7_defect rx link 0 defects rx link 1 defects rx link 2 defects rx link 3 defects rx link 4 defects rx link 5 defects rx link 6 defects rx link 7 defects page 237 0x898 0x899 0x89a 0x89b 0x89c 0x89d 0x89e 0x89f ima_fe_tx_lnk0_cfg ima_fe_tx_lnk1_cfg ima_fe_tx_lnk2_cfg ima_fe_tx_lnk3_cfg ima_fe_tx_lnk4_cfg ima_fe_tx_lnk5_cfg ima_fe_tx_lnk6_cfg ima_fe_tx_lnk7_cfg fe tx link 0 link config fe tx link 1 link config fe tx link 2 link config fe tx link 3 link config fe tx link 4 link config fe tx link 5 link config fe tx link 6 link config fe tx link 7 link config page 238 0x8a0 0x8a1 0x8a2 0x8a3 0x8a4 0x8a5 0x8a6 0x8a7 ima_fe_lnk0_state ima_fe_lnk1_state ima_fe_lnk2_state ima_fe_lnk3_state ima_fe_lnk4_state ima_fe_lnk5_state ima_fe_lnk6_state ima_fe_lnk7_state rx link 0 fe status rx link 1 fe status rx link 2 fe status rx link 3 fe status rx link 4 fe status rx link 5 fe status rx link 6 fe status rx link 7 fe status page 239 0x8a8 0x8a9 0x8aa 0x8ab 0x8ac 0x8ad 0x8ae 0x8af ima_rx_lnk0_id ima_rx_lnk1_id ima_rx_lnk2_id ima_rx_lnk3_id ima_rx_lnk4_id ima_rx_lnk5_id ima_rx_lnk6_id ima_rx_lnk7_id rx link 0 assigned lid rx link 1 assigned lid rx link 2 assigned lid rx link 3 assigned lid rx link 4 assigned lid rx link 5 assigned lid rx link 6 assigned lid rx link 7 assigned lid page 240 0x8b0 0x8b1 0x8b2 0x8b3 0x8b4 0x8b5 0x8b6 0x8b7 ima_rx_lnk0_iv_cnt ima_rx_lnk1_iv_cnt ima_rx_lnk2_iv_cnt ima_rx_lnk3_iv_cnt ima_rx_lnk4_iv_cnt ima_rx_lnk5_iv_cnt ima_rx_lnk6_iv_cnt ima_rx_lnk7_iv_cnt rx link 0 iv-ima counter rx link 1 iv-ima counter rx link 2 iv-ima counter rx link 3 iv-ima counter rx link 4 iv-ima counter rx link 5 iv-ima counter rx link 6 iv-ima counter rx link 7 iv-ima counter page 241 0x8b8 0x8b9 0x8ba 0x8bb 0x8bc 0x8bd 0x8be 0x8bf ima_rx_lnk0_oif_cnt ima_rx_lnk1_oif_cnt ima_rx_lnk2_oif_cnt ima_rx_lnk3_oif_cnt ima_rx_lnk4_oif_cnt ima_rx_lnk5_oif_cnt ima_rx_lnk6_oif_cnt ima_rx_lnk7_oif_cnt rx link 0 oif-ima counter rx link 1 oif-ima counter rx link 2 oif-ima counter rx link 3 oif-ima counter rx link 4 oif-ima counter rx link 5 oif-ima counter rx link 6 oif-ima counter rx link 7 oif-ima counter page 242 table 2-10. ima control and status registers (5 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 123 mindspeed proprietary and confidential 0x8c0 0x8c1 0x8c2 0x8c3 0x8c4 0x8c5 0x8c6 0x8c7 ima_fe_tx_lnk0_grp_id ima_fe_tx_lnk1_grp_id ima_fe_tx_lnk2_grp_id ima_fe_tx_lnk3_grp_id ima_fe_tx_lnk4_grp_id ima_fe_tx_lnk5_grp_id ima_fe_tx_lnk6_grp_id ima_fe_tx_lnk7_grp_id rx link 0 captured grp id rx link 1 captured grp id rx link 2 captured grp id rx link 3 captured grp id rx link 4 captured grp id rx link 5 captured grp id rx link 6 captured grp id rx link 7 captured grp id page 243 receive groups 1?4 configuration tables 0x8d0 ima_rx_grp1_cfg rx grp 1 configuration page 220 0x8d1 ima_rx_grp1_ctl rx grp 1 control page 221 0x8d2 ima_rx_grp1_first_phy_addr rx grp 1 first link address page 222 0x8d3 ima_rx_grp1_id rx grp 1 rx group id page 223 0x8d4 ima_rx_grp2_cfg rx grp 2 configuration page 220 0x8d5 ima_rx_grp2_ctl rx grp 2 control page 221 0x8d6 ima_rx_grp2_first_phy_addr rx grp 2 first link address page 222 0x8d7 ima_rx_grp2_id rx grp 2 rx group id page 223 0x8d8 ima_rx_grp3_cfg rx grp 3 configuration page 220 0x8d9 ima_rx_grp3_ctl rx grp 3 control page 221 0x8da ima_rx_grp3_first_phy_addr rx grp 3 first link address page 222 0x8db ima_rx_grp3_id rx grp 3 rx group id page 223 0x8dc ima_rx_grp4_cfg rx grp 4 configuration page 220 0x8dd ima_rx_grp4_ctl rx grp 4 control page 221 0x8de ima_rx_grp4_first_phy_addr rx grp 4 first link address page 222 0x8df ima_rx_grp4_id rx grp 4 rx group id page 223 receive groups 1?4 far-end status 0x8e0 ima_rx_grp1_rx_test_patter n rx grp 1 rx test pattern page 224 0x8e2 ima_rx_grp1_stat_ctl_change rx grp 1 scci page 225 0x8e3 ima_rx_grp1_actual_grp_id rx grp 1 rx group id page 226 0x8e4 ima_rx_grp1_stat_ctl rx grp 1 status / control page 227 0x8e5 ima_rx_grp1_timing_inf o rx grp 1 timing control page 228 0x8e6 ima_rx_grp1_test_ctl rx grp 1 test control page 229 0x8e7 ima_rx_grp1_tx_test_pattern rx grp 1 tx test pattern page 230 0x8e8 ima_rx_grp2_rx_test_patter n rx grp 2 rx test pattern page 224 0x8ea ima_rx_grp2_stat_ctl_change rx grp 2 scci page 225 0x8eb ima_rx_grp2_actual_grp_id rx grp 2 rx group id page 226 0x8ec ima_rx_grp2_stat_ctl rx grp 2 status / control page 227 table 2-10. ima control and status registers (6 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 124 mindspeed proprietary and confidential 0x8ed ima_rx_grp2_timing_inf o rx grp 2 timing control page 228 0x8ee ima_rx_grp2_test_ctl rx grp 2 test control page 229 0x8ef ima_rx_grp2_tx_test_pattern rx grp 2 tx test pattern page 230 0x8f0 ima_rx_grp3_rx_test_patter n rx grp 3 rx test pattern page 224 0x8f2 ima_rx_grp3_stat_ctl_change rx grp 3 scci page 225 0x8f3 ima_rx_grp3_actual_gr p_id rx grp 3 rx group id page 226 0x8f4 ima_rx_grp3_stat_ctl rx grp 3 status / control page 227 0x8f5 ima_rx_grp3_timing_inf o rx grp 3 timing control page 228 0x8f6 ima_rx_grp3_test_ctl rx grp 3 test control page 229 0x8f7 ima_rx_grp3_tx_test_pattern rx grp 3 tx test pattern page 230 0x8f8 ima_rx_grp4_rx_test_patter n rx grp 4 rx test pattern page 224 0x8fa ima_rx_grp4_stat_ctl_change rx grp 4 scci page 225 0x8fb ima_rx_grp4_actual_gr p_id rx grp 4 rx group id page 226 0x8fc ima_rx_grp4_stat_ctl rx grp 4 status / control page 227 0x8fd ima_rx_grp4_timing_inf o rx grp 4 timing control page 228 0x8fe ima_rx_grp4_test_ctl rx grp 4 test control page 229 0x8ff ima_rx_grp4_tx_test_pattern rx grp 4 tx test pattern page 230 transmit groups 5?8 configuration tables 0x920 ima_tx_grp5_rx_test_pattern tx grp 5 rx test pattern page 208 0x921 ima_tx_grp5_ctl tx grp 5 control page 209 0x922 ima_tx_grp5_first_phy_addr tx grp 5 first link address page 210 0x923 ima_tx_grp5_id tx grp 5 tx group id page 211 0x924 ima_tx_grp5_stat_ctl tx grp 5 status / control page 212 0x925 ima_tx_grp5_timing_inf o tx grp 5 timing control page 213 0x926 ima_tx_grp5_test_ctl tx grp 5 test control page 214 0x927 ima_tx_grp5_tx_test_pattern tx grp 5 tx test pattern page 215 0x928 ima_tx_grp6_rx_test_pattern tx grp 6 rx test pattern page 208 0x929 ima_tx_grp6_ctl tx grp 6 control page 209 0x92a ima_tx_grp6_first_phy_addr tx grp 6 first link address page 210 0x92b ima_tx_grp6_id tx grp 6 tx group id page 211 0x92c ima_tx_grp6_stat_ctl tx grp 6 status / control page 212 0x92d ima_tx_grp6_timing_inf o tx grp 6 timing control page 213 0x92e ima_tx_grp6_test_ctl tx grp 6 test control page 214 0x92f ima_tx_grp6_tx_test_pattern tx grp 6 tx test pattern page 215 0x930 ima_tx_grp7_rx_test_pattern tx grp 7 rx test pattern page 208 table 2-10. ima control and status registers (7 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 125 mindspeed proprietary and confidential 0x931 ima_tx_grp7_ctl tx grp 7 control page 209 0x932 ima_tx_grp7_first_phy_addr tx grp 7 first link address page 210 0x933 ima_tx_grp7_id tx grp 7 tx group id page 211 0x934 ima_tx_grp7_stat_ctl tx grp 7 status / control page 212 0x935 ima_tx_grp7_timing_inf o tx grp 7 timing control page 213 0x936 ima_tx_grp7_test_ctl tx grp 7 test control page 214 0x937 ima_tx_grp7_tx_test_pattern tx grp 7 tx test pattern page 215 0x938 ima_tx_grp8_rx_test_pattern tx grp 8 rx test pattern page 208 0x939 ima_tx_grp8_ctl tx grp 8 control page 209 0x93a ima_tx_grp8_first_phy_addr tx grp 8 first link address page 210 0x93b ima_tx_grp8_id tx grp 8 tx group id page 211 0x93c ima_tx_grp8_stat_ctl tx grp 8 status / control page 212 0x93d ima_tx_grp8_timing_inf o tx grp 8 timing control page 213 0x93e ima_tx_grp8_test_ctl tx grp 8 test control page 214 0x93f ima_tx_grp8_tx_test_pattern tx grp 8 tx test pattern page 215 tx utopia addresses 4 - 7 cell counters 0x940 0x941 0x942 0x943 0x944 0x945 0x946 0x947 ima_tx_atm4_cell_count_lsb ima_tx_atm4_cell_count_msb ima_tx_atm5_cell_count_lsb ima_tx_atm5_cell_count_msb ima_tx_atm6_cell_count_lsb ima_tx_atm6_cell_count_msb ima_tx_atm7_cell_count_lsb ima_tx_atm7_cell_count_msb transmit utopia address 0x04 cell count lsbs transmit utopia address 0x04 cell count msbs transmit utopia address 0x05 cell count lsbs transmit utopia address 0x05 cell count msbs transmit utopia address 0x06 cell count lsbs transmit utopia address 0x06 cell count msbs transmit utopia address 0x07 cell count lsbs transmit utopia address 0x07 cell count msbs page 216 rx utopia addresses 4 - 7 cell counters 0x950 0x951 0x952 0x953 0x954 0x955 0x956 0x957 ima_rx_atm4_cell_count_lsb ima_rx_atm4_cell_count_msb ima_rx_atm5_cell_count_lsb ima_rx_atm5_cell_count_msb ima_rx_atm6_cell_count_lsb ima_rx_atm6_cell_count_msb ima_rx_atm7_cell_count_lsb ima_rx_atm7_cell_count_msb receive utopia address 0x04 cell count lsbs receive utopia address 0x04 cell count msbs receive utopia address 0x05 cell count lsbs receive utopia address 0x05 cell count msbs receive utopia address 0x06 cell count lsbs receive utopia address 0x06 cell count msbs receive utopia address 0x07 cell count lsbs receive utopia address 0x07 cell count msbs page 218 table 2-10. ima control and status registers (8 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 126 mindspeed proprietary and confidential port 8?15 control and status 0x960 0x961 0x962 0x963 0x964 0x965 0x966 0x967 ima_tx_lnk8_ctl ima_tx_lnk9_ctl ima_tx_lnk10_ctl ima_tx_lnk11_ctl ima_tx_lnk12_ctl ima_tx_lnk13_ctl ima_tx_lnk14_ctl ima_tx_lnk15_ctl tx link 8 control tx link 9 control tx link 10 control tx link 11 control tx link 12 control tx link 13 control tx link 14 control tx link 15 control page 232 0x968 0x969 0x96a 0x96b 0x96c 0x96d 0x96e 0x96f ima_tx_lnk8_state ima_tx_lnk9_state ima_tx_lnk10_state ima_tx_lnk11_state ima_tx_lnk12_state ima_tx_lnk13_state ima_tx_lnk14_state ima_tx_lnk15_state tx link 8 status tx link 9 status tx link 10 status tx link 11 status tx link 12 status tx link 13 status tx link 14 status tx link 15 status page 233 0x970 0x971 0x972 0x973 0x974 0x975 0x976 0x977 ima_tx_lnk8_id ima_tx_lnk9_id ima_tx_lnk10_id ima_tx_lnk11_id ima_tx_lnk12_id ima_tx_lnk13_id ima_tx_lnk14_id ima_tx_lnk15_id tx link 8 assigned lid tx link 9 assigned lid tx link 10 assigned lid tx link 11 assigned lid tx link 12 assigned lid tx link 13 assigned lid tx link 14 assigned lid tx link 15 assigned lid page 234 0x980 0x981 0x982 0x983 0x984 0x985 0x986 0x987 ima_rx_lnk8_ctl ima_rx_lnk9_ctl ima_rx_lnk10_ctl ima_rx_lnk11_ctl ima_rx_lnk12_ctl ima_rx_lnk13_ctl ima_rx_lnk14_ctl ima_rx_lnk15_ctl rx link 8 control rx link 9 control rx link 10 control rx link 11 control rx link 12 control rx link 13 control rx link 14 control rx link 15 control page 235 0x988 0x989 0x98a 0x98b 0x98c 0x98d 0x98e 0x98f ima_rx_lnk8_state ima_rx_lnk9_state ima_rx_lnk10_state ima_rx_lnk11_state ima_rx_lnk12_state ima_rx_lnk13_state ima_rx_lnk14_state ima_rx_lnk15_state rx link 8 status rx link 9 status rx link 10 status rx link 11 status rx link 12 status rx link 13 status rx link 14 status rx link 15 status page 236 table 2-10. ima control and status registers (9 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 127 mindspeed proprietary and confidential 0x990 0x991 0x992 0x993 0x994 0x995 0x996 0x997 ima_rx_lnk8_defect ima_rx_lnk9_defect ima_rx_lnk10_defect ima_rx_lnk11_defect ima_rx_lnk12_defect ima_rx_lnk13_defect ima_rx_lnk14_defect ima_rx_lnk15_defect rx link 8 defects rx link 9 defects rx link 10 defects rx link 11 defects rx link 12 defects rx link 13 defects rx link 14 defects rx link 15 defects page 237 0x998 0x999 0x99a 0x99b 0x99c 0x99d 0x99e 0x99f ima_fe_tx_lnk8_cfg ima_fe_tx_lnk9_cfg ima_fe_tx_lnk10_cfg ima_fe_tx_lnk11_cfg ima_fe_tx_lnk12_cfg ima_fe_tx_lnk13_cfg ima_fe_tx_lnk14_cfg ima_fe_tx_lnk15_cfg fe tx link 8 link config fe tx link 9 link config fe tx link 10 link config fe tx link 11 link config fe tx link 12 link config fe tx link 13 link config fe tx link 14 link config fe tx link 15 link config page 238 0x9a0 0x9a1 0x9a2 0x9a3 0x9a4 0x9a5 0x9a6 0x9a7 ima_fe_lnk8_state ima_fe_lnk9_state ima_fe_lnk10_state ima_fe_lnk11_state ima_fe_lnk12_state ima_fe_lnk13_state ima_fe_lnk14_state ima_fe_lnk15_state rx link 8 fe status rx link 9 fe status rx link 10 fe status rx link 11 fe status rx link 12 fe status rx link 13 fe status rx link 14 fe status rx link 15 fe status page 239 0x9a8 0x9a9 0x9aa 0x9ab 0x9ac 0x9ad 0x9ae 0x9af ima_rx_lnk8_id ima_rx_lnk9_id ima_rx_lnk10_id ima_rx_lnk11_id ima_rx_lnk12_id ima_rx_lnk13_id ima_rx_lnk14_id ima_rx_lnk15_id rx link 8 assigned lid rx link 9 assigned lid rx link 10 assigned lid rx link 11 assigned lid rx link 12 assigned lid rx link 13 assigned lid rx link 14 assigned lid rx link 15 assigned lid page 240 0x9b0 0x9b1 0x9b2 0x9b3 0x9b4 0x9b5 0x9b6 0x9b7 ima_rx_lnk8_iv_cnt ima_rx_lnk9_iv_cnt ima_rx_lnk10_iv_cnt ima_rx_lnk11_iv_cnt ima_rx_lnk12_iv_cnt ima_rx_lnk13_iv_cnt ima_rx_lnk14_iv_cnt ima_rx_lnk15_iv_cnt rx link 8 iv-ima counter rx link 9 iv-ima counter rx link 10 iv-ima counter rx link 11 iv-ima counter rx link 12 iv-ima counter rx link 13 iv-ima counter rx link 14 iv-ima counter rx link 15 iv-ima counter page 241 0x9b8 0x9b9 0x9ba 0x9bb 0x9bc 0x9bd 0x9be 0x9bf ima_rx_lnk8_oif_cnt ima_rx_lnk9_oif_cnt ima_rx_lnk10_oif_cnt ima_rx_lnk11_oif_cnt ima_rx_lnk12_oif_cnt ima_rx_lnk13_oif_cnt ima_rx_lnk14_oif_cnt ima_rx_lnk15_oif_cnt rx link 8 oif-ima counter rx link 9 oif-ima counter rx link 10 oif-ima counter rx link 11 oif-ima counter rx link 12 oif-ima counter rx link 13 oif-ima counter rx link 14 oif-ima counter rx link 15 oif-ima counter page 242 table 2-10. ima control and status registers (10 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 128 mindspeed proprietary and confidential 0x9c0 0x9c1 0x9c2 0x9c3 0x9c4 0x9c5 0x9c6 0x9c7 ima_fe_tx_lnk8_grp_id ima_fe_tx_lnk9_grp_id ima_fe_tx_lnk10_grp_id ima_fe_tx_lnk11_grp_id ima_fe_tx_lnk12_grp_id ima_fe_tx_lnk13_grp_id ima_fe_tx_lnk14_grp_id ima_fe_tx_lnk15_grp_id rx link 8 captured grp id rx link 9 captured grp id rx link 10 captured grp id rx link 11 captured grp id rx link 12 captured grp id rx link 13 captured grp id rx link 14 captured grp id rx link 15 captured grp id page 243 receive groups 5?8 configuration tables 0x9d0 ima_rx_grp5_cfg rx grp 5 configuration page 220 0x9d1 ima_rx_grp5_ctl rx grp 5 control page 221 0x9d2 ima_rx_grp5_first_phy_addr rx grp 5 first link address page 222 0x9d3 ima_rx_grp5_id rx grp 5 rx group id page 223 0x9d4 ima_rx_grp6_cfg rx grp 6 configuration page 220 0x9d5 ima_rx_grp6_ctl rx grp 6 control page 221 0x9d6 ima_rx_grp6_first_phy_addr rx grp 6 first link address page 222 0x9d7 ima_rx_grp6_id rx grp 6 rx group id page 223 0x9d8 ima_rx_grp7_cfg rx grp 7 configuration page 220 0x9d9 ima_rx_grp7_ctl rx grp 7 control page 221 0x9da ima_rx_grp7_first_phy_addr rx grp 7 first link address page 222 0x9db ima_rx_grp7_id rx grp 7 rx group id page 223 0x9dc ima_rx_grp8_cfg rx grp 8 configuration page 220 0x9dd ima_rx_grp8_ctl rx grp 8 control page 221 0x9de ima_rx_grp8_first_phy_addr rx grp 8 first link address page 222 0x9df ima_rx_grp8_id rx grp 8 rx group id page 223 receive groups 5?8 far-end status 0x9e0 ima_rx_grp5_rx_test_patter n rx grp 5 rx test pattern page 224 0x9e2 ima_rx_grp5_stat_ctl_change rx grp 5 scci page 225 0x9e3 ima_rx_grp5_actual_grp_id rx grp 5 rx group id page 226 0x9e4 ima_rx_grp5_stat_ctl rx grp 5 status / control page 227 0x9e5 ima_rx_grp5_timing_inf o rx grp 5 timing control page 228 0x9e6 ima_rx_grp5_test_ctl rx grp 5 test control page 229 0x9e7 ima_rx_grp5_tx_test_pattern rx grp 5 tx test pattern page 230 0x9e8 ima_rx_grp6_rx_test_patter n rx grp 6 rx test pattern page 224 0x9ea ima_rx_grp6_stat_ctl_change rx grp 6 scci page 225 0x9eb ima_rx_grp6_actual_grp_id rx grp 6 rx group id page 226 0x9ec ima_rx_grp6_stat_ctl rx grp 6 status / control page 227 table 2-10. ima control and status registers (11 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 129 mindspeed proprietary and confidential 0x9ed ima_rx_grp6_timing_inf o rx grp 6 timing control page 228 0x9ee ima_rx_grp6_test_ctl rx grp 6 test control page 229 0x9ef ima_rx_grp6_tx_test_pattern rx grp 6 tx test pattern page 230 0x9f0 ima_rx_grp7_rx_test_patter n rx grp 7 rx test pattern page 224 0x9f2 ima_rx_grp7_stat_ctl_change rx grp 7 scci page 225 0x9f3 ima_rx_grp7_actual_gr p_id rx grp 7 rx group id page 226 0x9f4 ima_rx_grp7_stat_ctl rx grp 7 status / control page 227 0x9f5 ima_rx_grp7_timing_inf o rx grp 7 timing control page 228 0x9f6 ima_rx_grp7_test_ctl rx grp 7 test control page 229 0x9f7 ima_rx_grp7_tx_test_pattern rx grp 7 tx test pattern page 230 0x9f8 ima_rx_grp8_rx_test_patter n rx grp 8 rx test pattern page 224 0x9fa ima_rx_grp8_stat_ctl_change rx grp 8 scci page 225 0x9fb ima_rx_grp8_actual_gr p_id rx grp 8 rx group id page 226 0x9fc ima_rx_grp8_stat_ctl rx grp 8 status / control page 227 0x9fd ima_rx_grp8_timing_inf o rx grp 8 timing control page 228 0x9fe ima_rx_grp8_test_ctl rx grp 8 test control page 229 0x9ff ima_rx_grp8_tx_test_pattern rx grp 8 tx test pattern page 230 transmit groups 9?12 configuration tables 0xa20 ima_tx_grp9_rx_test_pattern tx grp 9 rx test pattern page 208 0xa21 ima_tx_grp9_ctl tx grp 9 control page 209 0xa22 ima_tx_grp9_first_phy_addr tx grp 9 first link address page 210 0xa23 ima_tx_grp9_id tx grp 9 tx group id page 211 0xa24 ima_tx_grp9_stat_ctl tx grp 9 status / control page 212 0xa25 ima_tx_grp9_timing_inf o tx grp 9 timing control page 213 0xa26 ima_tx_grp9_test_ctl tx grp 9 test control page 214 0xa27 ima_tx_grp9_tx_test_pattern tx grp 9 tx test pattern page 215 0xa28 ima_tx_grp10_rx_test_pattern tx grp 10 rx test pattern page 208 0xa29 ima_tx_grp10_ctl tx grp 10 control page 209 0xa2a ima_tx_grp10_first_phy_addr tx grp 10 first link address page 210 0xa2b ima_tx_grp10_id tx grp 10 tx group id page 211 0xa2c ima_tx_grp10_stat_ctl tx grp 10 status / control page 212 0xa2d ima_tx_grp10_timing_info tx grp 10 timing control page 213 0xa2e ima_tx_grp10_test_ctl tx grp 10 test control page 214 0xa2f ima_tx_grp10_tx_test_pattern tx grp 10 tx test pattern page 215 0xa30 ima_tx_grp11_rx_test_pattern tx grp 11 rx test pattern page 208 table 2-10. ima control and status registers (12 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 130 mindspeed proprietary and confidential 0xa31 ima_tx_grp11_ctl tx grp 11 control page 209 0xa32 ima_tx_grp11_first_phy_addr tx grp 11 first link address page 210 0xa33 ima_tx_grp11_id tx grp 11 tx group id page 211 0xa34 ima_tx_grp11_stat_ctl tx grp 11 status / control page 212 0xa35 ima_tx_grp11_timing_info tx grp 11 timing control page 213 0xa36 ima_tx_grp11_test_ctl tx grp 11 test control page 214 0xa37 ima_tx_grp11_tx_test_pattern tx grp 11 tx test pattern page 215 0xa38 ima_tx_grp12_rx_test_pattern tx grp 12 rx test pattern page 208 0xa39 ima_tx_grp12_ctl tx grp 12 control page 209 0xa3a ima_tx_grp12_first_phy_addr tx grp 12 first link address page 210 0xa3b ima_tx_grp12_id tx grp 12 tx group id page 211 0xa3c ima_tx_grp12_stat_ctl tx grp 12 status / control page 212 0xa3d ima_tx_grp12_timing_info tx grp 12 timing control page 213 0xa3e ima_tx_grp12_test_ctl tx grp 12 test control page 214 0xa3f ima_tx_grp12_tx_test_pattern tx grp 12 tx test pattern page 215 tx utopia addresses 8 - 11 cell counters 0xa40 0xa41 0xa42 0xa43 0xa44 0xa45 0xa46 0xa47 ima_tx_atm8_cell_count_lsb ima_tx_atm8_cell_count_msb ima_tx_atm9_cell_count_lsb ima_tx_atm9_cell_count_msb ima_tx_atm10_cell_count_lsb ima_tx_atm10_cell_count_msb ima_tx_atm11_cell_count_lsb ima_tx_atm11_cell_count_msb transmit utopia address 0x08 cell count lsbs transmit utopia address 0x08 cell count msbs transmit utopia address 0x09 cell count lsbs transmit utopia address 0x09 cell count msbs transmit utopia address 0x0a cell count lsbs transmit utopia address 0x0a cell count msbs transmit utopia address 0x0b cell count lsbs transmit utopia address 0x0b cell count msbs page 216 rx utopia addresses 8 - 11 cell counters 0xa50 0xa51 0xa52 0xa53 0xa54 0xa55 0xa56 0xa57 ima_rx_atm8_cell_count_lsb ima_rx_atm8_cell_count_msb ima_rx_atm9_cell_count_lsb ima_rx_atm9_cell_count_msb ima_rx_atm10_cell_count_lsb ima_rx_atm10_cell_count_msb ima_rx_atm11_cell_count_lsb ima_rx_atm11_cell_count_msb receive utopia address 0x08 cell count lsbs receive utopia address 0x08 cell count msbs receive utopia address 0x09 cell count lsbs receive utopia address 0x09 cell count msbs receive utopia address 0x0a cell count lsbs receive utopia address 0x0a cell count msbs receive utopia address 0x0b cell count lsbs receive utopia address 0x0b cell count msbs page 218 table 2-10. ima control and status registers (13 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 131 mindspeed proprietary and confidential port 16?23 control and status 0xa60 0xa61 0xa62 0xa63 0xa64 0xa65 0xa66 0xa67 ima_tx_lnk16_ctl ima_tx_lnk17_ctl ima_tx_lnk18_ctl ima_tx_lnk19_ctl ima_tx_lnk20_ctl ima_tx_lnk21_ctl ima_tx_lnk22_ctl ima_tx_lnk23_ctl tx link 16 control tx link 17 control tx link 18 control tx link 19 control tx link 20 control tx link 21 control tx link 22 control tx link 23 control page 232 0xa68 0xa69 0xa6a 0xa6b 0xa6c 0xa6d 0xa6e 0xa6f ima_tx_lnk16_state ima_tx_lnk17_state ima_tx_lnk18_state ima_tx_lnk19_state ima_tx_lnk20_state ima_tx_lnk21_state ima_tx_lnk22_state ima_tx_lnk23_state tx link 16 status tx link 17 status tx link 18 status tx link 19 status tx link 20 status tx link 21 status tx link 22 status tx link 23 status page 233 0xa70 0xa71 0xa72 0xa73 0xa74 0xa75 0xa76 0xa77 ima_tx_lnk16_id ima_tx_lnk17_id ima_tx_lnk18_id ima_tx_lnk19_id ima_tx_lnk20_id ima_tx_lnk21_id ima_tx_lnk22_id ima_tx_lnk23_id tx link 16 assigned lid tx link 17 assigned lid tx link 18 assigned lid tx link 19 assigned lid tx link 20 assigned lid tx link 21 assigned lid tx link 22 assigned lid tx link 23 assigned lid page 234 0xa80 0xa81 0xa82 0xa83 0xa84 0xa85 0xa86 0xa87 ima_rx_lnk16_ctl ima_rx_lnk17_ctl ima_rx_lnk18_ctl ima_rx_lnk19_ctl ima_rx_lnk20_ctl ima_rx_lnk21_ctl ima_rx_lnk22_ctl ima_rx_lnk23_ctl rx link 16 control rx link 17 control rx link 18 control rx link 19 control rx link 20 control rx link 21 control rx link 22 control rx link 23 control page 235 0xa88 0xa89 0xa8a 0xa8b 0xa8c 0xa8d 0xa8e 0xa8f ima_rx_lnk16_state ima_rx_lnk17_state ima_rx_lnk18_state ima_rx_lnk19_state ima_rx_lnk20_state ima_rx_lnk21_state ima_rx_lnk22_state ima_rx_lnk23_state rx link 16 status rx link 17 status rx link 18 status rx link 19 status rx link 20 status rx link 21 status rx link 22 status rx link 23 status page 236 table 2-10. ima control and status registers (14 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 132 mindspeed proprietary and confidential 0xa90 0xa91 0xa92 0xa93 0xa94 0xa95 0xa96 0xa97 ima_rx_lnk16_defect ima_rx_lnk17_defect ima_rx_lnk18_defect ima_rx_lnk19_defect ima_rx_lnk20_defect ima_rx_lnk21_defect ima_rx_lnk22_defect ima_rx_lnk23_defect rx link 16 defects rx link 17 defects rx link 18 defects rx link 19 defects rx link 20 defects rx link 21 defects rx link 22 defects rx link 23 defects page 237 0xa98 0xa99 0xa9a 0xa9b 0xa9c 0xa9d 0xa9e 0xa9f ima_fe_tx_lnk16_cfg ima_fe_tx_lnk17_cfg ima_fe_tx_lnk18_cfg ima_fe_tx_lnk19_cfg ima_fe_tx_lnk20_cfg ima_fe_tx_lnk21_cfg ima_fe_tx_lnk22_cfg ima_fe_tx_lnk23_cfg fe tx link 16 link config fe tx link 17 link config fe tx link 18 link config fe tx link 19 link config fe tx link 20 link config fe tx link 21 link config fe tx link 22 link config fe tx link 23 link config page 238 0xaa0 0xaa1 0xaa2 0xaa3 0xaa4 0xaa5 0xaa6 0xaa7 ima_fe_lnk16_state ima_fe_lnk17_state ima_fe_lnk18_state ima_fe_lnk19_state ima_fe_lnk20_state ima_fe_lnk21_state ima_fe_lnk22_state ima_fe_lnk23_state rx link 16 fe status rx link 17 fe status rx link 18 fe status rx link 19 fe status rx link 20 fe status rx link 21 fe status rx link 22 fe status rx link 23 fe status page 239 0xaa8 0xaa9 0xaaa 0xaab 0xaac 0xaad 0xaae 0xaaf ima_rx_lnk16_id ima_rx_lnk17_id ima_rx_lnk18_id ima_rx_lnk19_id ima_rx_lnk20_id ima_rx_lnk21_id ima_rx_lnk22_id ima_rx_lnk23_id rx link 16 assigned lid rx link 17 assigned lid rx link 18 assigned lid rx link 19 assigned lid rx link 20 assigned lid rx link 21 assigned lid rx link 22 assigned lid rx link 23 assigned lid page 240 0xab0 0xab1 0xab2 0xab3 0xab4 0xab5 0xab6 0xab7 ima_rx_lnk16_iv_cnt ima_rx_lnk17_iv_cnt ima_rx_lnk18_iv_cnt ima_rx_lnk19_iv_cnt ima_rx_lnk20_iv_cnt ima_rx_lnk21_iv_cnt ima_rx_lnk22_iv_cnt ima_rx_lnk23_iv_cnt rx link 16 iv-ima counter rx link 17 iv-ima counter rx link 18 iv-ima counter rx link 19 iv-ima counter rx link 20 iv-ima counter rx link 21 iv-ima counter rx link 22 iv-ima counter rx link 23 iv-ima counter page 241 0xab8 0xab9 0xaba 0xabb 0xabc 0xabd 0xabe 0xabf ima_rx_lnk16_oif_cnt ima_rx_lnk17_oif_cnt ima_rx_lnk18_oif_cnt ima_rx_lnk19_oif_cnt ima_rx_lnk20_oif_cnt ima_rx_lnk21_oif_cnt ima_rx_lnk22_oif_cnt ima_rx_lnk23_oif_cnt rx link 16 oif-ima counter rx link 17 oif-ima counter rx link 18 oif-ima counter rx link 19 oif-ima counter rx link 20 oif-ima counter rx link 21 oif-ima counter rx link 22 oif-ima counter rx link 23 oif-ima counter page 242 table 2-10. ima control and status registers (15 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 133 mindspeed proprietary and confidential 0xac0 0xac1 0xac2 0xac3 0xac4 0xac5 0xac6 0xac7 ima_fe_tx_lnk16_grp_id ima_fe_tx_lnk17_grp_id ima_fe_tx_lnk18_grp_id ima_fe_tx_lnk19_grp_id ima_fe_tx_lnk20_grp_id ima_fe_tx_lnk21_grp_id ima_fe_tx_lnk22_grp_id ima_fe_tx_lnk23_grp_id rx link 16 captured grp id rx link 17 captured grp id rx link 18 captured grp id rx link 19 captured grp id rx link 20 captured grp id rx link 21 captured grp id rx link 22 captured grp id rx link 23 captured grp id page 243 receive groups 9?12 configuration tables 0xad0 ima_rx_grp9_cfg rx grp 9 configuration page 220 0xad1 ima_rx_grp9_ctl rx grp 9 control page 221 0xad2 ima_rx_grp9_first_phy_addr rx grp 9 first link address page 222 0xad3 ima_rx_grp9_id rx grp 9 rx group id page 223 0xad4 ima_rx_grp10_cfg rx grp 10 configuration page 220 0xad5 ima_rx_grp10_ctl rx grp 10 control page 221 0xad6 ima_rx_grp10_first_phy_addr rx grp 10 first link address page 222 0xad7 ima_rx_grp10_id rx grp 10 rx group id page 223 0xad8 ima_rx_grp11_cfg rx grp 11 configuration page 220 0xad9 ima_rx_grp11_ctl rx grp 11 control page 221 0xada ima_rx_grp11_first_phy_addr rx grp 11 first link address page 222 0xadb ima_rx_grp11_id rx grp 11 rx group id page 223 0xadc ima_rx_grp12_cfg rx grp 12 configuration page 220 0xadd ima_rx_grp12_ctl rx grp 12 control page 221 0xade ima_rx_grp12_first_phy_addr rx grp 12 first link address page 222 0xadf ima_rx_grp12_id rx grp 12 rx group id page 223 receive groups 9?12 far-end status 0xae0 ima_rx_grp9_rx_test_pattern rx grp 9 rx test pattern page 224 0xae2 ima_rx_grp9_stat_ctl_change rx grp 9 scci page 225 0xae3 ima_rx_grp9_actual_grp_id rx grp 9 rx group id page 226 0xae4 ima_rx_grp9_stat_ctl rx grp 9 status / control page 227 0xae5 ima_rx_grp9_timing_info rx grp 9 timing control page 228 0xae6 ima_rx_grp9_test_ctl rx grp 9 test control page 229 0xae7 ima_rx_grp9_tx_test_pattern rx grp 9 tx test pattern page 230 0xae8 ima_rx_grp10_rx_test_pattern rx grp 10 rx test pattern page 224 0xaea ima_rx_grp10_stat_ctl_change rx grp 10 scci page 225 0xaeb ima_rx_grp10_actual_grp_id rx grp 10 rx group id page 226 0xaec ima_rx_grp10_stat_ctl rx grp 10 status / control page 227 table 2-10. ima control and status registers (16 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 134 mindspeed proprietary and confidential 0xaed ima_rx_grp10_timing_info rx grp 10 timing control page 228 0xaee ima_rx_grp10_test_ctl rx grp 10 test control page 229 0xaef ima_rx_grp10_tx_test_pattern rx grp 10 tx test pattern page 230 0xaf0 ima_rx_grp11_rx_test_patter n rx grp 11 rx test pattern page 224 0xaf2 ima_rx_grp11_stat_ctl_change rx grp 11 scci page 225 0xaf3 ima_rx_grp11_actual_grp_id rx grp 11 rx group id page 226 0xaf4 ima_rx_grp11_stat_ctl rx grp 11 status / control page 227 0xaf5 ima_rx_grp11_timing_info rx grp 11 timing control page 228 0xaf6 ima_rx_grp11_test_ctl rx grp 11 test control page 229 0xaf7 ima_rx_grp11_tx_test_patter n rx grp 11 tx test pattern page 230 0xaf8 ima_rx_grp12_rx_test_patter n rx grp 12 rx test pattern page 224 0xafa ima_rx_grp12_stat_ctl_change rx grp 12 scci page 225 0xafb ima_rx_grp12_actual_grp_id rx grp 12 rx group id page 226 0xafc ima_rx_grp12_stat_ctl rx grp 12 status / control page 227 0xafd ima_rx_grp12_timing_info rx grp 12 timing control page 228 0xafe ima_rx_grp12_test_ctl rx grp 12 test control page 229 0xaff ima_rx_grp12_tx_test_patter n rx grp 12 tx test pattern page 230 transmit groups 13?16 configuration tables 0xb20 ima_tx_grp13_rx_test_pattern tx grp 13 rx test pattern page 208 0xb21 ima_tx_grp13_ctl tx grp 13 control page 209 0xb22 ima_tx_grp13_first_phy_addr tx grp 13 first link address page 210 0xb23 ima_tx_grp13_id tx grp 13 tx group id page 211 0xb24 ima_tx_grp13_stat_ctl tx grp 13 status / control page 212 0xb25 ima_tx_grp13_timing_info tx grp 13 timing control page 213 0xb26 ima_tx_grp13_test_ctl tx grp 13 test control page 214 0xb27 ima_tx_grp13_tx_test_pattern tx grp 13 tx test pattern page 215 0xb28 ima_tx_grp14_rx_test_pattern tx grp 14 rx test pattern page 208 0xb29 ima_tx_grp14_ctl tx grp 14 control page 209 0xb2a ima_tx_grp14_first_phy_addr tx grp 14 first link address page 210 0xb2b ima_tx_grp14_id tx grp 14 tx group id page 211 0xb2c ima_tx_grp14_stat_ctl tx grp 14 status / control page 212 0xb2d ima_tx_grp14_timing_info tx grp 14 timing control page 213 0xb2e ima_tx_grp14_test_ctl tx grp 14 test control page 214 0xb2f ima_tx_grp14_tx_test_pattern tx grp 14 tx test pattern page 215 0xb30 ima_tx_grp15_rx_test_pattern tx grp 15 rx test pattern page 208 table 2-10. ima control and status registers (17 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 135 mindspeed proprietary and confidential 0xb31 ima_tx_grp15_ctl tx grp 15 control page 209 0xb32 ima_tx_grp15_first_phy_addr tx grp 15 first link address page 210 0xb33 ima_tx_grp15_id tx grp 15 tx group id page 211 0xb34 ima_tx_grp15_stat_ctl tx grp 15 status / control page 212 0xb35 ima_tx_grp15_timing_info tx grp 15 timing control page 213 0xb36 ima_tx_grp15_test_ctl tx grp 15 test control page 214 0xb37 ima_tx_grp15_tx_test_pattern tx grp 15 tx test pattern page 215 0xb38 ima_tx_grp16_rx_test_pattern tx grp 16 rx test pattern page 208 0xb39 ima_tx_grp16_ctl tx grp 16 control page 209 0xb3a ima_tx_grp16_first_phy_addr tx grp 16 first link address page 210 0xb3b ima_tx_grp16_id tx grp 16 tx group id page 211 0xb3c ima_tx_grp16_stat_ctl tx grp 16 status / control page 212 0xb3d ima_tx_grp16_timing_info tx grp 16 timing control page 213 0xb3e ima_tx_grp16_test_ctl tx grp 16 test control page 214 0xb3f ima_tx_grp16_tx_test_pattern tx grp 16 tx test pattern page 215 tx utopia addresses 12 - 15 cell counters 0xb40 0xb41 0xb42 0xb43 0xb44 0xb45 0xb46 0xb47 ima_tx_atm12_cell_count_lsb ima_tx_atm12_cell_count_msb ima_tx_atm13_cell_count_lsb ima_tx_atm13_cell_count_msb ima_tx_atm14_cell_count_lsb ima_tx_atm14_cell_count_msb ima_tx_atm15_cell_count_lsb ima_tx_atm15_cell_count_msb transmit utopia address 0x0c cell count lsbs transmit utopia address 0x0c cell count msbs transmit utopia address 0x0d cell count lsbs transmit utopia address 0x0d cell count msbs transmit utopia address 0x0e cell count lsbs transmit utopia address 0x0e cell count msbs transmit utopia address 0x0f cell count lsbs transmit utopia address 0x0f cell count msbs page 216 rx utopia addresses 12 - 15 cell counters 0xb50 0xb51 0xb52 0xb53 0xb54 0xb55 0xb56 0xb57 ima_rx_atm12_cell_count_lsb ima_rx_atm12_cell_count_msb ima_rx_atm13_cell_count_lsb ima_rx_atm13_cell_count_msb ima_rx_atm14_cell_count_lsb ima_rx_atm14_cell_count_msb ima_rx_atm15_cell_count_lsb ima_rx_atm15_cell_count_msb receive utopia address 0x0c cell count lsbs receive utopia address 0x0c cell count msbs receive utopia address 0x0d cell count lsbs receive utopia address 0x0d cell count msbs receive utopia address 0x0e cell count lsbs receive utopia address 0x0e cell count msbs receive utopia address 0x0f cell count lsbs receive utopia address 0x0f cell count msbs page 218 table 2-10. ima control and status registers (18 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 136 mindspeed proprietary and confidential port 24?31 control and status 0xb60 0xb61 0xb62 0xb63 0xb64 0xb65 0xb66 0xb67 ima_tx_lnk24_ctl ima_tx_lnk25_ctl ima_tx_lnk26_ctl ima_tx_lnk27_ctl ima_tx_lnk28_ctl ima_tx_lnk29_ctl ima_tx_lnk30_ctl ima_tx_lnk31_ctl tx link 24 control tx link 25 control tx link 26 control tx link 27 control tx link 28 control tx link 29 control tx link 30 control tx link 31 control page 232 0xb68 0xb69 0xb6a 0xb6b 0xb6c 0xb6d 0xb6e 0xb6f ima_tx_lnk24_state ima_tx_lnk25_state ima_tx_lnk26_state ima_tx_lnk27_state ima_tx_lnk28_state ima_tx_lnk29_state ima_tx_lnk30_state ima_tx_lnk31_state tx link 24 status tx link 25 status tx link 26 status tx link 27 status tx link 28 status tx link 29 status tx link 30 status tx link 31 status page 233 0xb70 0xb71 0xb72 0xb73 0xb74 0xb75 0xb76 0xb77 ima_tx_lnk24_id ima_tx_lnk25_id ima_tx_lnk26_id ima_tx_lnk27_id ima_tx_lnk28_id ima_tx_lnk29_id ima_tx_lnk30_id ima_tx_lnk31_id tx link 24 assigned lid tx link 25 assigned lid tx link 26 assigned lid tx link 27 assigned lid tx link 28 assigned lid tx link 29 assigned lid tx link 30 assigned lid tx link 31 assigned lid page 234 0xb80 0xb81 0xb82 0xb83 0xb84 0xb85 0xb86 0xb87 ima_rx_lnk24_ctl ima_rx_lnk25_ctl ima_rx_lnk26_ctl ima_rx_lnk27_ctl ima_rx_lnk28_ctl ima_rx_lnk29_ctl ima_rx_lnk30_ctl ima_rx_lnk31_ctl rx link 24 control rx link 25 control rx link 26 control rx link 27 control rx link 28 control rx link 29 control rx link 30 control rx link 31 control page 235 0xb88 0xb89 0xb8a 0xb8b 0xb8c 0xb8d 0xb8e 0xb8f ima_rx_lnk24_state ima_rx_lnk25_state ima_rx_lnk26_state ima_rx_lnk27_state ima_rx_lnk28_state ima_rx_lnk29_state ima_rx_lnk30_state ima_rx_lnk31_state rx link 24 status rx link 25 status rx link 26 status rx link 27 status rx link 28 status rx link 29 status rx link 30 status rx link 31 status page 236 table 2-10. ima control and status registers (19 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 137 mindspeed proprietary and confidential 0xb90 0xb91 0xb92 0xb93 0xb94 0xb95 0xb96 0xb97 ima_rx_lnk24_defect ima_rx_lnk25_defect ima_rx_lnk26_defect ima_rx_lnk27_defect ima_rx_lnk28_defect ima_rx_lnk29_defect ima_rx_lnk30_defect ima_rx_lnk31_defect rx link 24 defects rx link 25 defects rx link 26 defects rx link 27 defects rx link 28 defects rx link 29 defects rx link 30 defects rx link 31 defects page 237 0xb98 0xb99 0xb9a 0xb9b 0xb9c 0xb9d 0xb9e 0xb9f ima_fe_tx_lnk24_cfg ima_fe_tx_lnk25_cfg ima_fe_tx_lnk26_cfg ima_fe_tx_lnk27_cfg ima_fe_tx_lnk28_cfg ima_fe_tx_lnk29_cfg ima_fe_tx_lnk30_cfg ima_fe_tx_lnk31_cfg fe tx link 24 link config fe tx link 25 link config fe tx link 26 link config fe tx link 27 link config fe tx link 28 link config fe tx link 29 link config fe tx link 30 link config fe tx link 31 link config page 238 0xba0 0xba1 0xba2 0xba3 0xba4 0xba5 0xba6 0xba7 ima_fe_lnk24_state ima_fe_lnk25_state ima_fe_lnk26_state ima_fe_lnk27_state ima_fe_lnk28_state ima_fe_lnk29_state ima_fe_lnk30_state ima_fe_lnk31_state rx link 24 fe status rx link 25 fe status rx link 26 fe status rx link 27 fe status rx link 28 fe status rx link 29 fe status rx link 30 fe status rx link 31 fe status page 239 0xba8 0xba9 0xbaa 0xbab 0xbac 0xbad 0xbae 0xbaf ima_rx_lnk24_id ima_rx_lnk25_id ima_rx_lnk26_id ima_rx_lnk27_id ima_rx_lnk28_id ima_rx_lnk29_id ima_rx_lnk30_id ima_rx_lnk31_id rx link 24 assigned lid rx link 25 assigned lid rx link 26 assigned lid rx link 27 assigned lid rx link 28 assigned lid rx link 29 assigned lid rx link 30 assigned lid rx link 31 assigned lid page 240 0xbb0 0xbb1 0xbb2 0xbb3 0xbb4 0xbb5 0xbb6 0xbb7 ima_rx_lnk24_iv_cnt ima_rx_lnk25_iv_cnt ima_rx_lnk26_iv_cnt ima_rx_lnk27_iv_cnt ima_rx_lnk28_iv_cnt ima_rx_lnk29_iv_cnt ima_rx_lnk30_iv_cnt ima_rx_lnk31_iv_cnt rx link 24 iv-ima counter rx link 25 iv-ima counter rx link 26 iv-ima counter rx link 27 iv-ima counter rx link 28 iv-ima counter rx link 29 iv-ima counter rx link 30 iv-ima counter rx link 31 iv-ima counter page 241 0xbb8 0xbb9 0xbba 0xbbb 0xbbc 0xbbd 0xbbe 0xbbf ima_rx_lnk24_oif_cnt ima_rx_lnk25_oif_cnt ima_rx_lnk26_oif_cnt ima_rx_lnk27_oif_cnt ima_rx_lnk28_oif_cnt ima_rx_lnk29_oif_cnt ima_rx_lnk30_oif_cnt ima_rx_lnk31_oif_cnt rx link 24 oif-ima counter rx link 25 oif-ima counter rx link 26 oif-ima counter rx link 27 oif-ima counter rx link 28 oif-ima counter rx link 29 oif-ima counter rx link 30 oif-ima counter rx link 31 oif-ima counter page 242 table 2-10. ima control and status registers (20 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 138 mindspeed proprietary and confidential 0xbc0 0xbc1 0xbc2 0xbc3 0xbc4 0xbc5 0xbc6 0xbc7 ima_fe_tx_lnk24_grp_id ima_fe_tx_lnk25_grp_id ima_fe_tx_lnk26_grp_id ima_fe_tx_lnk27_grp_id ima_fe_tx_lnk28_grp_id ima_fe_tx_lnk29_grp_id ima_fe_tx_lnk30_grp_id ima_fe_tx_lnk31_grp_id rx link 24 captured grp id rx link 25 captured grp id rx link 26 captured grp id rx link 27 captured grp id rx link 28 captured grp id rx link 29 captured grp id rx link 30 captured grp id rx link 31 captured grp id page 243 receive groups 13?16 configuration tables 0xbd0 ima_rx_grp13_cfg rx grp 13 configuration page 220 0xbd1 ima_rx_grp13_ctl rx grp 13 control page 221 0xbd2 ima_rx_grp13_first_phy_addr rx grp 13 first link address page 222 0xbd3 ima_rx_grp13_id rx grp 13 rx group id page 223 0xbd4 ima_rx_grp14_cfg rx grp 14 configuration page 220 0xbd5 ima_rx_grp14_ctl rx grp 14 control page 221 0xbd6 ima_rx_grp14_first_phy_addr rx grp 14 first link address page 222 0xbd7 ima_rx_grp14_id rx grp 14 rx group id page 223 0xbd8 ima_rx_grp15_cfg rx grp 15 configuration page 220 0xbd9 ima_rx_grp15_ctl rx grp 15 control page 221 0xbda ima_rx_grp15_first_phy_addr rx grp 15 first link address page 222 0xbdb ima_rx_grp15_id rx grp 15 rx group id page 223 0xbdc ima_rx_grp16_cfg rx grp 16 configuration page 220 0xbdd ima_rx_grp16_ctl rx grp 16 control page 221 0xbde ima_rx_grp16_first_phy_addr rx grp 16 first link address page 222 0xbdf ima_rx_grp16_id rx grp 16 rx group id page 223 receive groups 13?16 far-end status 0xbe0 ima_rx_grp13_rx_test_patter n rx grp 13 rx test pattern page 224 0xbe2 ima_rx_grp13_stat_ctl_change rx grp 13 scci page 225 0xbe3 ima_rx_grp13_actual_grp_id rx grp 13 rx group id page 226 0xbe4 ima_rx_grp13_stat_ctl rx grp 13 status / control page 227 0xbe5 ima_rx_grp13_timing_info rx grp 13 timing control page 228 0xbe6 ima_rx_grp13_test_ctl rx grp 13 test control page 229 0xbe7 ima_rx_grp13_tx_test_patter n rx grp 13 tx test pattern page 230 0xbe8 ima_rx_grp14_rx_test_patter n rx grp 14 rx test pattern page 224 0xbea ima_rx_grp14_stat_ctl_change rx grp 14 scci page 225 0xbeb ima_rx_grp14_actual_grp_id rx grp 14 rx group id page 226 0xbec ima_rx_grp14_stat_ctl rx grp 14 status / control page 227 table 2-10. ima control and status registers (21 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 139 mindspeed proprietary and confidential 0xbed ima_rx_grp14_timing_info rx grp 14 timing control page 228 0xbee ima_rx_grp14_test_ctl rx grp 14 test control page 229 0xbef ima_rx_grp14_tx_test_patter n rx grp 14 tx test pattern page 230 0xbf0 ima_rx_grp15_rx_test_patter n rx grp 15 rx test pattern page 224 0xbf2 ima_rx_grp15_stat_ctl_change rx grp 15 scci page 225 0xbf3 ima_rx_grp15_actual_g rp_id rx grp 15 rx group id page 226 0xbf4 ima_rx_grp15_stat_ctl rx grp 15 status / control page 227 0xbf5 ima_rx_grp15_timing_info rx grp 15 timing control page 228 0xbf6 ima_rx_grp15_test_ctl rx grp 15 test control page 229 0xbf7 ima_rx_grp15_tx_test_patter n rx grp 15 tx test pattern page 230 0xbf8 ima_rx_grp16_rx_test_patter n rx grp 16 rx test pattern page 224 0xbfa ima_rx_grp16_stat_ctl_change rx grp 16 scci page 225 0xbfb ima_rx_grp16_actual_g rp_id rx grp 16 rx group id page 226 0xbfc ima_rx_grp12_stat_ctl rx grp 16 status / control page 227 0xbfd ima_rx_grp16_timing_info rx grp 16 timing control page 228 0xbfe ima_rx_grp16_test_ctl rx grp 16 test control page 229 0xbff ima_rx_grp16_tx_test_patter n rx grp 16 tx test pattern page 230 transmit groups 17?20 configuration tables 0xc20 ima_tx_grp17_rx_test_pattern tx grp 17 rx test pattern page 208 0xc21 ima_tx_grp17_ctl tx grp 17 control page 209 0xc22 ima_tx_grp17_first_phy_addr tx grp 17 first link address page 210 0xc23 ima_tx_grp17_id tx grp 17 tx group id page 211 0xc24 ima_tx_grp17_stat_ctl tx grp 17 status / control page 212 0xc25 ima_tx_grp17_timing_info tx grp 17 timing control page 213 0xc26 ima_tx_grp17_test_ctl tx grp 17 test control page 214 0xc27 ima_tx_grp17_tx_test_pattern tx grp 17 tx test pattern page 215 0xc28 ima_tx_grp18_rx_test_pattern tx grp 18 rx test pattern page 208 0xc29 ima_tx_grp18_ctl tx grp 18 control page 209 0xc2a ima_tx_grp18_first_phy_addr tx grp 18 first link address page 210 0xc2b ima_tx_grp18_id tx grp 18 tx group id page 211 0xc2c ima_tx_grp18_stat_ctl tx grp 18 status / control page 212 0xc2d ima_tx_grp18_timing_info tx grp 18 timing control page 213 0xc2e ima_tx_grp18_test_ctl tx grp 18 test control page 214 0xc2f ima_tx_grp18_tx_test_pattern tx grp 18 tx test pattern page 215 0xc30 ima_tx_grp19_rx_test_pattern tx grp 19 rx test pattern page 208 table 2-10. ima control and status registers (22 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 140 mindspeed proprietary and confidential 0xc31 ima_tx_grp19_ctl tx grp 19 control page 209 0xc32 ima_tx_grp19_first_phy_addr tx grp 19 first link address page 210 0xc33 ima_tx_grp19_id tx grp 19 tx group id page 211 0xc34 ima_tx_grp19_stat_ctl tx grp 19 status / control page 212 0xc35 ima_tx_grp19_timing_info tx grp 19 timing control page 213 0xc36 ima_tx_grp19_test_ctl tx grp 19 test control page 214 0xc37 ima_tx_grp19_tx_test_pattern tx grp 19 tx test pattern page 215 0xc38 ima_tx_grp20_rx_test_pattern tx grp 20 rx test pattern page 208 0xc39 ima_tx_grp20_ctl tx grp 20 control page 209 0xc3a ima_tx_grp20_first_phy_addr tx grp 20 first link address page 210 0xc3b ima_tx_grp20_id tx grp 20 tx group id page 211 0xc3c ima_tx_grp20_stat_ctl tx grp 20 status / control page 212 0xc3d ima_tx_grp20_timing_info tx grp 20 timing control page 213 0xc3e ima_tx_grp20_test_ctl tx grp 20 test control page 214 0xc3f ima_tx_grp20_tx_test_pattern tx grp 20 tx test pattern page 215 tx utopia addresses 16 - 19 cell counters 0xc40 0xc41 0xc42 0xc43 0xc44 0xc45 0xc46 0xc47 ima_tx_atm16_cell_count_lsb ima_tx_atm16_cell_count_msb ima_tx_atm17_cell_count_lsb ima_tx_atm17_cell_count_msb ima_tx_atm18_cell_count_lsb ima_tx_atm18_cell_count_msb ima_tx_atm19_cell_count_lsb ima_tx_atm19_cell_count_msb transmit utopia address 0x10 cell count lsbs transmit utopia address 0x10 cell count msbs transmit utopia address 0x11 cell count lsbs transmit utopia address 0x11 cell count msbs transmit utopia address 0x12 cell count lsbs transmit utopia address 0x12 cell count msbs transmit utopia address 0x13 cell count lsbs transmit utopia address 0x13 cell count msbs page 216 rx utopia addresses 16 - 19 cell counters 0xc48 0xc49 0xc4a 0xc4b 0xc4c 0xc4d 0xc4e 0xc4f ima_rx_atm16_cell_count_lsb ima_rx_atm16_cell_count_msb ima_rx_atm17_cell_count_lsb ima_rx_atm17_cell_count_msb ima_rx_atm18_cell_count_lsb ima_rx_atm18_cell_count_msb ima_rx_atm19_cell_count_lsb ima_rx_atm19_cell_count_msb receive utopia address 0x10 cell count lsbs receive utopia address 0x10 cell count msbs receive utopia address 0x11 cell count lsbs receive utopia address 0x11 cell count msbs receive utopia address 0x12 cell count lsbs receive utopia address 0x12 cell count msbs receive utopia address 0x13 cell count lsbs receive utopia address 0x13 cell count msbs page 218 receive groups 17?20 configuration tables 0xc50 ima_rx_grp17_cfg rx grp 17 configuration page 220 0xc51 ima_rx_grp17_ctl rx grp 17 control page 221 0xc52 ima_rx_grp17_first_phy_addr rx grp 17 first link address page 222 0xc53 ima_rx_grp17_id rx grp 17 rx group id page 223 0xc54 ima_rx_grp18_cfg rx grp 18 configuration page 220 table 2-10. ima control and status registers (23 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 141 mindspeed proprietary and confidential 0xc55 ima_rx_grp18_ctl rx grp 18 control page 221 0xc56 ima_rx_grp18_first_phy_addr rx grp 18 first link address page 222 0xc57 ima_rx_grp18_id rx grp 18 rx group id page 223 0xc58 ima_rx_grp19_cfg rx grp 19 configuration page 220 0xc59 ima_rx_grp19_ctl rx grp 19 control page 221 0xc5a ima_rx_grp19_first_phy_addr rx grp 19 first link address page 222 0xc5b ima_rx_grp19_id rx grp 19 rx group id page 223 0xc5c ima_rx_grp20_cfg rx grp 20 configuration page 220 0xc5d ima_rx_grp20_ctl rx grp 20 control page 221 0xc5e ima_rx_grp20_first_phy_addr rx grp 20 first link address page 222 0xc5f ima_rx_grp20_id rx grp 20 rx group id page 223 receive groups 17?20 far-end status 0xc60 ima_rx_grp17_rx_test_patter n rx grp 17 rx test pattern page 224 0xc62 ima_rx_grp17_stat_ctl_change rx grp 17 scci page 225 0xc63 ima_rx_grp17_actual_grp_id rx grp 17 rx group id page 226 0xc64 ima_rx_grp17_stat_ctl rx grp 17 status / control page 227 0xc65 ima_rx_grp17_timing_info rx grp 17 timing control page 228 0xc66 ima_rx_grp17_test_ctl rx grp 17 test control page 229 0xc67 ima_rx_grp17_tx_test_patter n rx grp 17 tx test pattern page 230 0xc68 ima_rx_grp18_rx_test_patter n rx grp 18 rx test pattern page 224 0xc6a ima_rx_grp18_stat_ctl_change rx grp 18 scci page 225 0xc6b ima_rx_grp18_actual_grp_id rx grp 18 rx group id page 226 0xc6c ima_rx_grp18_stat_ctl rx grp 18 status / control page 227 0xc6d ima_rx_grp18_timing_info rx grp 18 timing control page 228 0xc6e ima_rx_grp18_test_ctl rx grp 18 test control page 229 0xc6f ima_rx_grp18_tx_test_patter n rx grp 18 tx test pattern page 230 0xc70 ima_rx_grp19_rx_test_patter n rx grp 19 rx test pattern page 224 0xc72 ima_rx_grp19_stat_ctl_change rx grp 19 scci page 225 0xc73 ima_rx_grp19_actual_grp_id rx grp 19 rx group id page 226 0xc74 ima_rx_grp19_stat_ctl rx grp 19 status / control page 227 0xc75 ima_rx_grp19_timing_info rx grp 19 timing control page 228 0xc76 ima_rx_grp19_test_ctl rx grp 19 test control page 229 0xc77 ima_rx_grp19_tx_test_patter n rx grp 19 tx test pattern page 230 0xc78 ima_rx_grp20_rx_test_patter n rx grp 20 rx test pattern page 224 0xc7a ima_rx_grp20_stat_ctl_change rx grp 20 scci page 225 table 2-10. ima control and status registers (24 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 142 mindspeed proprietary and confidential 0xc7b ima_rx_grp20_actual_grp_id rx grp 20 rx group id page 226 0xc7c ima_rx_grp20_stat_ctl rx grp 20 status / control page 227 0xc7d ima_rx_grp20_timing_info rx grp 20 timing control page 228 0xc7e ima_rx_grp20_test_ctl rx grp 20 test control page 229 0xc7f ima_rx_grp20_tx_test_patter n rx grp 20 tx test pattern page 230 transmit groups 21?24 configuration tables 0xca0 ima_tx_grp21_rx_test_pattern tx grp 21 rx test pattern page 208 0xca1 ima_tx_grp21_ctl tx grp 21 control page 209 0xca2 ima_tx_grp21_first_phy_addr tx grp 21 first link address page 210 0xca3 ima_tx_grp21_id tx grp 21 tx group id page 211 0xca4 ima_tx_grp21_stat_ctl tx grp 21 status / control page 212 0xca5 ima_tx_grp21_timing_info tx grp 21 timing control page 213 0xca6 ima_tx_grp21_test_ctl tx grp 21 test control page 214 0xca7 ima_tx_grp21_tx_test_pattern tx grp 21 tx test pattern page 215 0xca8 ima_tx_grp22_rx_test_pattern tx grp 22 rx test pattern page 208 0xca9 ima_tx_grp22_ctl tx grp 22 control page 209 0xcaa ima_tx_grp22_first_phy_addr tx grp 22 first link address page 210 0xcab ima_tx_grp22_id tx grp 22 tx group id page 211 0xcac ima_tx_grp22_stat_ctl tx grp 22 status / control page 212 0xcad ima_tx_grp22_timing_info tx grp 22 timing control page 213 0xcae ima_tx_grp22_test_ctl tx grp 22 test control page 214 0xcaf ima_tx_grp22_tx_test_pattern tx grp 22 tx test pattern page 215 0xcb0 ima_tx_grp23_rx_test_pattern tx grp 23 rx test pattern page 208 0xcb1 ima_tx_grp23_ctl tx grp 23 control page 209 0xcb2 ima_tx_grp23_first_phy_addr tx grp 23 first link address page 210 0xcb3 ima_tx_grp23_id tx grp 23 tx group id page 211 0xcb4 ima_tx_grp23_stat_ctl tx grp 23 status / control page 212 0xcb5 ima_tx_grp23_timing_info tx grp 23 timing control page 213 0xcb6 ima_tx_grp23_test_ctl tx grp 23 test control page 214 0xcb7 ima_tx_grp23_tx_test_pattern tx grp 23 tx test pattern page 215 0xcb8 ima_tx_grp24_rx_test_pattern tx grp 24 rx test pattern page 208 0xcb9 ima_tx_grp24_ctl tx grp 24 control page 209 0xcba ima_tx_grp24_first_phy_addr tx grp 24 first link address page 210 0xcbb ima_tx_grp24_id tx grp 24 tx group id page 211 0xcbc ima_tx_grp24_stat_ctl tx grp 24 status / control page 212 table 2-10. ima control and status registers (25 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 143 mindspeed proprietary and confidential 0xcbd ima_tx_grp24_timing_info tx grp 24 timing control page 213 0xcbe ima_tx_grp24_test_ctl tx grp 24 test control page 214 0xcbf ima_tx_grp24_tx_test_pattern tx grp 24 tx test pattern page 215 tx utopia addresses 20 - 23 cell counters 0xcc0 0xcc1 0xcc2 0xcc3 0xcc4 0xcc5 0xcc6 0xcc7 ima_tx_atm20_cell_count_lsb ima_tx_atm20_cell_count_msb ima_tx_atm21_cell_count_lsb ima_tx_atm21_cell_count_msb ima_tx_atm22_cell_count_lsb ima_tx_atm22_cell_count_msb ima_tx_atm23_cell_count_lsb ima_tx_atm23_cell_count_msb transmit utopia address 0x14 cell count lsbs transmit utopia address 0x14 cell count msbs transmit utopia address 0x15 cell count lsbs transmit utopia address 0x15 cell count msbs transmit utopia address 0x16 cell count lsbs transmit utopia address 0x16 cell count msbs transmit utopia address 0x17 cell count lsbs transmit utopia address 0x17 cell count msbs page 216 rx utopia addresses 20 - 23 cell counters 0xcc8 0xcc9 0xcca 0xccb 0xccc 0xccd 0xcce 0xccf ima_rx_atm20_cell_count_lsb ima_rx_atm20_cell_count_msb ima_rx_atm21_cell_count_lsb ima_rx_atm21_cell_count_msb ima_rx_atm22_cell_count_lsb ima_rx_atm22_cell_count_msb ima_rx_atm23_cell_count_lsb ima_rx_atm23_cell_count_msb receive utopia address 0x14 cell count lsbs receive utopia address 0x14 cell count msbs receive utopia address 0x15 cell count lsbs receive utopia address 0x15 cell count msbs receive utopia address 0x16 cell count lsbs receive utopia address 0x16 cell count msbs receive utopia address 0x17 cell count lsbs receive utopia address 0x17 cell count msbs page 218 receive groups 21?24 configuration tables 0xcd0 ima_rx_grp21_cfg rx grp 21 configuration page 220 0xcd1 ima_rx_grp21_ctl rx grp 21 control page 221 0xcd2 ima_rx_grp21_first_phy_addr rx grp 21 first link address page 222 0xcd3 ima_rx_grp21_id rx grp 21 rx group id page 223 0xcd4 ima_rx_grp22_cfg rx grp 22 configuration page 220 0xcd5 ima_rx_grp22_ctl rx grp 22 control page 221 0xcd6 ima_rx_grp22_first_phy_addr rx grp 22 first link address page 222 0xcd7 ima_rx_grp22_id rx grp 22 rx group id page 223 0xcd8 ima_rx_grp23_cfg rx grp 23 configuration page 220 0xcd9 ima_rx_grp23_ctl rx grp 23 control page 221 0xcda ima_rx_grp23_first_phy_addr rx grp 23 first link address page 222 0xcdb ima_rx_grp23_id rx grp 23 rx group id page 223 0xcdc ima_rx_grp24_cfg rx grp 24 configuration page 220 0xcdd ima_rx_grp24_ctl rx grp 24 control page 221 0xcde ima_rx_grp24_first_phy_addr rx grp 24 first link address page 222 0xcdf ima_rx_grp24_id rx grp 24 rx group id page 223 table 2-10. ima control and status registers (26 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 144 mindspeed proprietary and confidential receive groups 21?24 far-end status 0xce0 ima_rx_grp21_rx_test_pattern rx grp 21 rx test pattern page 224 0xce2 ima_rx_grp21_stat_ctl_change rx grp 21 scci page 225 0xce3 ima_rx_grp21_actual_grp_id rx grp 21 rx group id page 226 0xce4 ima_rx_grp21_stat_ctl rx grp 21 status / control page 227 0xce5 ima_rx_grp21_timing_info rx grp 21 timing control page 228 0xce6 ima_rx_grp21_test_ctl rx grp 21 test control page 229 0xce7 ima_rx_grp21_tx_test_pattern rx grp 21 tx test pattern page 230 0xce8 ima_rx_grp22_rx_test_pattern rx grp 22 rx test pattern page 224 0xcea ima_rx_grp22_stat_ctl_change rx grp 22 scci page 225 0xceb ima_rx_grp22_actual_grp_id rx grp 22 rx group id page 226 0xcec ima_rx_grp22_stat_ctl rx grp 22 status / control page 227 0xced ima_rx_grp22_timing_info rx grp 22 timing control page 228 0xcee ima_rx_grp22_test_ctl rx grp 22 test control page 229 0xcef ima_rx_grp22_tx_test_pattern rx grp 22 tx test pattern page 230 0xcf0 ima_rx_grp23_rx_test_patter n rx grp 23 rx test pattern page 224 0xcf2 ima_rx_grp23_stat_ctl_change rx grp 23 scci page 225 0xcf3 ima_rx_grp23_actual_grp_id rx grp 23 rx group id page 226 0xcf4 ima_rx_grp23_stat_ctl rx grp 23 status / control page 227 0xcf5 ima_rx_grp23_timing_info rx grp 23 timing control page 228 0xcf6 ima_rx_grp23_test_ctl rx grp 23 test control page 229 0xcf7 ima_rx_grp23_tx_test_patter n rx grp 23 tx test pattern page 230 0xcf8 ima_rx_grp24_rx_test_patter n rx grp 24 rx test pattern page 224 0xcfa ima_rx_grp24_stat_ctl_change rx grp 24 scci page 225 0xcfb ima_rx_grp24_actual_grp_id rx grp 24 rx group id page 226 0xcfc ima_rx_grp24_stat_ctl rx grp 24 status / control page 227 0xcfd ima_rx_grp24_timing_info rx grp 24 timing control page 228 0xcfe ima_rx_grp24_test_ctl rx grp 24 test control page 229 0xcff ima_rx_grp24_tx_test_patter n rx grp 24 tx test pattern page 230 transmit groups 25?28 configuration tables 0xd20 ima_tx_grp25_rx_test_pattern tx grp 25 rx test pattern page 208 0xd21 ima_tx_grp25_ctl tx grp 25 control page 209 0xd22 ima_tx_grp25_first_phy_addr tx grp 25 first link address page 210 0xd23 ima_tx_grp25_id tx grp 25 tx group id page 211 0xd24 ima_tx_grp25_stat_ctl tx grp 25 status / control page 212 table 2-10. ima control and status registers (27 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 145 mindspeed proprietary and confidential 0xd25 ima_tx_grp25_timing_info tx grp 25 timing control page 213 0xd26 ima_tx_grp25_test_ctl tx grp 25 test control page 214 0xd27 ima_tx_grp25_tx_test_pattern tx grp 25 tx test pattern page 215 0xd28 ima_tx_grp26_rx_test_pattern tx grp 26 rx test pattern page 208 0xd29 ima_tx_grp26_ctl tx grp 26 control page 209 0xd2a ima_tx_grp26_first_phy_addr tx grp 26 first link address page 210 0xd2b ima_tx_grp26_id tx grp 26 tx group id page 211 0xd2c ima_tx_grp26_stat_ctl tx grp 26 status / control page 212 0xd2d ima_tx_grp26_timing_info tx grp 26 timing control page 213 0xd2e ima_tx_grp26_test_ctl tx grp 26 test control page 214 0xd2f ima_tx_grp26_tx_test_pattern tx grp 26 tx test pattern page 215 0xd30 ima_tx_grp27_rx_test_pattern tx grp 27 rx test pattern page 208 0xd31 ima_tx_grp27_ctl tx grp 27 control page 209 0xd32 ima_tx_grp27_first_phy_addr tx grp 27 first link address page 210 0xd33 ima_tx_grp27_id tx grp 27 tx group id page 211 0xd34 ima_tx_grp27_stat_ctl tx grp 27 status / control page 212 0xd35 ima_tx_grp27_timing_info tx grp 27 timing control page 213 0xd36 ima_tx_grp27_test_ctl tx grp 27 test control page 214 0xd37 ima_tx_grp27_tx_test_pattern tx grp 27 tx test pattern page 215 0xd38 ima_tx_grp28_rx_test_pattern tx grp 28 rx test pattern page 208 0xd39 ima_tx_grp28_ctl tx grp 28 control page 209 0xd3a ima_tx_grp28_first_phy_addr tx grp 28 first link address page 210 0xd3b ima_tx_grp28_id tx grp 28 tx group id page 211 0xd3c ima_tx_grp28_stat_ctl tx grp 28 status / control page 212 0xd3d ima_tx_grp28_timing_info tx grp 28 timing control page 213 0xd3e ima_tx_grp28_test_ctl tx grp 28 test control page 214 0xd3f ima_tx_grp28_tx_test_pattern tx grp 28 tx test pattern page 215 tx utopia addresses 24 - 27 cell counters 0xd40 0xd41 0xd42 0xd43 0xd44 0xd45 0xd46 0xd47 ima_tx_atm24_cell_count_lsb ima_tx_atm24_cell_count_msb ima_tx_atm25_cell_count_lsb ima_tx_atm25_cell_count_msb ima_tx_atm26_cell_count_lsb ima_tx_atm26_cell_count_msb ima_tx_atm27_cell_count_lsb ima_tx_atm27_cell_count_msb transmit utopia address 0x18 cell count lsbs transmit utopia address 0x18 cell count msbs transmit utopia address 0x19 cell count lsbs transmit utopia address 0x19 cell count msbs transmit utopia address 0x1a cell count lsbs transmit utopia address 0x1a cell count msbs transmit utopia address 0x1b cell count lsbs transmit utopia address 0x1b cell count msbs page 216 table 2-10. ima control and status registers (28 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 146 mindspeed proprietary and confidential rx utopia addresses 24 - 27 cell counters 0xd48 0xd49 0xd4a 0xd4b 0xd4c 0xd4d 0xd4e 0xd4f ima_rx_atm24_cell_count_lsb ima_rx_atm24_cell_count_msb ima_rx_atm25_cell_count_lsb ima_rx_atm25_cell_count_msb ima_rx_atm26_cell_count_lsb ima_rx_atm26_cell_count_msb ima_rx_atm27_cell_count_lsb ima_rx_atm27_cell_count_msb receive utopia address 0x18 cell count lsbs receive utopia address 0x18 cell count msbs receive utopia address 0x19 cell count lsbs receive utopia address 0x19 cell count msbs receive utopia address 0x1a cell count lsbs receive utopia address 0x1a cell count msbs receive utopia address 0x1b cell count lsbs receive utopia address 0x1b cell count msbs page 218 receive groups 25?28 configuration tables 0xd50 ima_rx_grp25_cfg rx grp 25 configuration page 220 0xd51 ima_rx_grp25_ctl rx grp 25 control page 221 0xd52 ima_rx_grp25_first_phy_addr rx grp 25 first link address page 222 0xd53 ima_rx_grp25_id rx grp 25 rx group id page 223 0xd54 ima_rx_grp26_cfg rx grp 26 configuration page 220 0xd55 ima_rx_grp26_ctl rx grp 26 control page 221 0xd56 ima_rx_grp26_first_phy_addr rx grp 26 first link address page 222 0xd57 ima_rx_grp26_id rx grp 26 rx group id page 223 0xd58 ima_rx_grp27_cfg rx grp 27 configuration page 220 0xd59 ima_rx_grp27_ctl rx grp 27 control page 221 0xd5a ima_rx_grp27_first_phy_addr rx grp 27 first link address page 222 0xd5b ima_rx_grp27_id rx grp 27 rx group id page 223 0xd5c ima_rx_grp28_cfg rx grp 28 configuration page 220 0xd5d ima_rx_grp28_ctl rx grp 28 control page 221 0xd5e ima_rx_grp28_first_phy_addr rx grp 28 first link address page 222 0xd5f ima_rx_grp28_id rx grp 28 rx group id page 223 receive groups 25?28 far-end status 0xd60 ima_rx_grp25_rx_test_patter n rx grp 25 rx test pattern page 224 0xd62 ima_rx_grp25_stat_ctl_change rx grp 25 scci page 225 0xd63 ima_rx_grp25_actual_grp_id rx grp 25 rx group id page 226 0xd64 ima_rx_grp25_stat_ctl rx grp 25 status / control page 227 0xd65 ima_rx_grp25_timing_info rx grp 25 timing control page 228 0xd66 ima_rx_grp25_test_ctl rx grp 25 test control page 229 0xd67 ima_rx_grp25_tx_test_patter n rx grp 25 tx test pattern page 230 0xd68 ima_rx_grp26_rx_test_patter n rx grp 26 rx test pattern page 224 0xd6a ima_rx_grp26_stat_ctl_change rx grp 26 scci page 225 0xd6b ima_rx_grp26_actual_grp_id rx grp 26 rx group id page 226 table 2-10. ima control and status registers (29 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 147 mindspeed proprietary and confidential 0xd6c ima_rx_grp26_stat_ctl rx grp 26 status / control page 227 0xd6d ima_rx_grp26_timing_info rx grp 26 timing control page 228 0xd6e ima_rx_grp26_test_ctl rx grp 26 test control page 229 0xd6f ima_rx_grp26_tx_test_pattern rx grp 26 tx test pattern page 230 0xd70 ima_rx_grp27_rx_test_patter n rx grp 27 rx test pattern page 224 0xd72 ima_rx_grp27_stat_ctl_change rx grp 27 scci page 225 0xd73 ima_rx_grp27_actual_grp_id rx grp 27 rx group id page 226 0xd74 ima_rx_grp27_stat_ctl rx grp 27 status / control page 227 0xd75 ima_rx_grp27_timing_info rx grp 27 timing control page 228 0xd76 ima_rx_grp27_test_ctl rx grp 27 test control page 229 0xd77 ima_rx_grp27_tx_test_patter n rx grp 27 tx test pattern page 230 0xd78 ima_rx_grp28_rx_test_patter n rx grp 28 rx test pattern page 224 0xd7a ima_rx_grp28_stat_ctl_change rx grp 28 scci page 225 0xd7b ima_rx_grp28_actual_grp_id rx grp 28 rx group id page 226 0xd7c ima_rx_grp28_stat_ctl rx grp 28 status / control page 227 0xd7d ima_rx_grp28_timing_info rx grp 28 timing control page 228 0xd7e ima_rx_grp28_test_ctl rx grp 28 test control page 229 0xd7f ima_rx_grp28_tx_test_pattern rx grp 28 tx test pattern page 230 transmit groups 29?32 configuration tables 0xda0 ima_tx_grp29_rx_test_pattern tx grp 29 rx test pattern page 208 0xda1 ima_tx_grp29_ctl tx grp 29 control page 209 0xda2 ima_tx_grp29_first_phy_addr tx grp 29 first link address page 210 0xda3 ima_tx_grp29_id tx grp 29 tx group id page 211 0xda4 ima_tx_grp29_stat_ctl tx grp 29 status / control page 212 0xda5 ima_tx_grp29_timing_info tx grp 29 timing control page 213 0xda6 ima_tx_grp29_test_ctl tx grp 29 test control page 214 0xda7 ima_tx_grp29_tx_test_pattern tx grp 29 tx test pattern page 215 0xda8 ima_tx_grp30_rx_test_pattern tx grp 30 rx test pattern page 208 0xda9 ima_tx_grp30_ctl tx grp 30 control page 209 0xdaa ima_tx_grp30_first_phy_addr tx grp 30 first link address page 210 0xdab ima_tx_grp30_id tx grp 30 tx group id page 211 0xdac ima_tx_grp30_stat_ctl tx grp 30 status / control page 212 0xdad ima_tx_grp30_timing_info tx grp 30 timing control page 213 0xdae ima_tx_grp30_test_ctl tx grp 30 test control page 214 0xdaf ima_tx_grp30_tx_test_pattern tx grp 30 tx test pattern page 215 table 2-10. ima control and status registers (30 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 148 mindspeed proprietary and confidential 0xdb0 ima_tx_grp31_rx_test_pattern tx grp 31 rx test pattern page 208 0xdb1 ima_tx_grp31_ctl tx grp 31 control page 209 0xdb2 ima_tx_grp31_first_phy_addr tx grp 31 first link address page 210 0xdb3 ima_tx_grp31_id tx grp 31 tx group id page 211 0xdb4 ima_tx_grp31_stat_ctl tx grp 31 status / control page 212 0xdb5 ima_tx_grp31_timing_info tx grp 31 timing control page 213 0xdb6 ima_tx_grp31_test_ctl tx grp 31 test control page 214 0xdb7 ima_tx_grp31_tx_test_pattern tx grp 31 tx test pattern page 215 0xdb8 ima_tx_grp32_rx_test_pattern tx grp 32 rx test pattern page 208 0xdb9 ima_tx_grp32_ctl tx grp 32 control page 209 0xdba ima_tx_grp32_first_phy_addr tx grp 32 first link address page 210 0xdbb ima_tx_grp32_id tx grp 32 tx group id page 211 0xdbc ima_tx_grp32_stat_ctl tx grp 32 status / control page 212 0xdbd ima_tx_grp32_timing_info tx grp 32 timing control page 213 0xdbe ima_tx_grp32_test_ctl tx grp 32 test control page 214 0xdbf ima_tx_grp32_tx_test_pattern tx grp 32 tx test pattern page 215 tx utopia addresses 28 - 31 cell counters 0xdc0 0xdc1 0xdc2 0xdc3 0xdc4 0xdc5 0xdc6 0xdc7 ima_tx_atm28_cell_count_lsb ima_tx_atm28_cell_count_msb ima_tx_atm29_cell_count_lsb ima_tx_atm29_cell_count_msb ima_tx_atm30_cell_count_lsb ima_tx_atm30_cell_count_msb ima_tx_atm31_cell_count_lsb ima_tx_atm31_cell_count_msb transmit utopia address 0x1c cell count lsbs transmit utopia address 0x1c cell count msbs transmit utopia address 0x1d cell count lsbs transmit utopia address 0x1d cell count msbs transmit utopia address 0x1e cell count lsbs transmit utopia address 0x1e cell count msbs transmit utopia address 0x1f cell count lsbs transmit utopia address 0x1f cell count msbs page 216 rx utopia addresses 28 - 31 cell counters 0xdc8 0xdc9 0xdca 0xdcb 0xdcc 0xdcd 0xdce 0xdcf ima_rx_atm28_cell_count_lsb ima_rx_atm28_cell_count_msb ima_rx_atm29_cell_count_lsb ima_rx_atm29_cell_count_msb ima_rx_atm30_cell_count_lsb ima_rx_atm30_cell_count_msb ima_rx_atm31_cell_count_lsb ima_rx_atm31_cell_count_msb receive utopia address 0x1c cell count lsbs receive utopia address 0x1c cell count msbs receive utopia address 0x1d cell count lsbs receive utopia address 0x1d cell count msbs receive utopia address 0x1e cell count lsbs receive utopia address 0x1e cell count msbs receive utopia address 0x1f cell count lsbs receive utopia address 0x1f cell count msbs page 218 receive groups 29?32 configuration tables 0xdd0 ima_rx_grp29_cfg rx grp 29 configuration page 220 0xdd1 ima_rx_grp29_ctl rx grp 29 control page 221 0xdd2 ima_rx_grp29_first_phy_addr rx grp 29 first link address page 222 0xdd3 ima_rx_grp29_id rx grp 29 rx group id page 223 table 2-10. ima control and status registers (31 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 149 mindspeed proprietary and confidential 0xdd4 ima_rx_grp30_cfg rx grp 30 configuration page 220 0xdd5 ima_rx_grp30_ctl rx grp 30 control page 221 0xdd6 ima_rx_grp30_first_phy_addr rx grp 30 first link address page 222 0xdd7 ima_rx_grp30_id rx grp 30 rx group id page 223 0xdd8 ima_rx_grp31_cfg rx grp 31 configuration page 220 0xdd9 ima_rx_grp31_ctl rx grp 31 control page 221 0xdda ima_rx_grp31_first_phy_addr rx grp 31 first link address page 222 0xddb ima_rx_grp31_id rx grp 31 rx group id page 223 0xddc ima_rx_grp32_cfg rx grp 32 configuration page 220 0xddd ima_rx_grp32_ctl rx grp 32 control page 221 0xdde ima_rx_grp32_first_phy_addr rx grp 32 first link address page 222 0xddf ima_rx_grp32_id rx grp 32 rx group id page 223 receive groups 29?32 far-end status 0xde0 ima_rx_grp29_rx_test_patter n rx grp 29 rx test pattern page 224 0xde2 ima_rx_grp29_stat_ctl_change rx grp 29 scci page 225 0xde3 ima_rx_grp29_actual_grp_id rx grp 29 rx group id page 226 0xde4 ima_rx_grp29_stat_ctl rx grp 29 status / control page 227 0xde5 ima_rx_grp29_timing_info rx grp 29 timing control page 228 0xde6 ima_rx_grp29_test_ctl rx grp 29 test control page 229 0xde7 ima_rx_grp29_tx_test_patter n rx grp 29 tx test pattern page 230 0xde8 ima_rx_grp30_rx_test_patter n rx grp 30 rx test pattern page 224 0xdea ima_rx_grp30_stat_ctl_change rx grp 30 scci page 225 0xdeb ima_rx_grp30_actual_grp_id rx grp 30 rx group id page 226 0xdec ima_rx_grp30_stat_ctl rx grp 30 status / control page 227 0xded ima_rx_grp30_timing_info rx grp 30 timing control page 228 0xdee ima_rx_grp30_test_ctl rx grp 30 test control page 229 0xdef ima_rx_grp30_tx_test_patter n rx grp 30 tx test pattern page 230 0xdf0 ima_rx_grp31_rx_test_patter n rx grp 31 rx test pattern page 224 0xdf2 ima_rx_grp31_stat_ctl_change rx grp 31 scci page 225 0xdf3 ima_rx_grp31_actual_g rp_id rx grp 31 rx group id page 226 0xdf4 ima_rx_grp31_stat_ctl rx grp 31 status / control page 227 0xdf5 ima_rx_grp31_timing_info rx grp 31 timing control page 228 0xdf6 ima_rx_grp31_test_ctl rx grp 31 test control page 229 0xdf7 ima_rx_grp31_tx_test_patter n rx grp 31 tx test pattern page 230 0xdf8 ima_rx_grp32_rx_test_patter n rx grp 32 rx test pattern page 224 table 2-10. ima control and status registers (32 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 150 mindspeed proprietary and confidential 2.2 tc registers 2.2.1 0x00?sumint (summary interru pt indication status register) the sumint register indicates the one-second interrupts, external framer interrupts, and port summary interrupts. 0xdfa ima_rx_grp32_stat_ctl_change rx grp 32 scci page 225 0xdfb ima_rx_grp32_actual_g rp_id rx grp 32 rx group id page 226 0xdfc ima_rx_grp32_stat_ctl rx grp 32 status / control page 227 0xdfd ima_rx_grp32_timing_info rx grp 32 timing control page 228 0xdfe ima_rx_grp32_test_ctl rx grp 32 test control page 229 0xdff ima_rx_grp32_tx_test_patter n rx grp 32 tx test pattern page 230 atm cell capture registers 0xe00- 0xe2f cell_cap_payldn cell capture payload contents registers page 244 0xe30 cap_fac capture facility register page 244 0xe31 cap_cntl capture control register page 244 0xe32 cap_stat capture status register page 245 bit default name description 7 0 ? reserved, set to a logical 0. 6 0 ? reserved, set to a logical 0. 5 0 ? reserved, set to a logical 0. 4 0 ? reserved, set to a logical 0. 3 0 ? reserved, set to a logical 0 2 0 ? reserved, set to a logical 0. 1?txcellint (1) when a logical 1 is read, this bi t indicates a transmit cell interr upt. this interrupt is a summary interrupt and signifies that an interrupt indicatio n occurred in the txcellint register (0x2c). 0?rxcellint (1) when a logical 1 is read, this bit indicates a receive cell interr upt. this interrupt is a summary interrupt and signifies that an interrupt indicatio n occurred in the rxcellint register (0x2d). footnote: (1) this bit is a summary i ndication of any interrupt events th at occurred in the indicated regi sters. this bit is a pointer to the next interrupt indication register to be read. this bit will be cleared when the interrupt bi ts in the corresponding interrupt indication regi sters are read and automatically cleared. table 2-10. ima control and status registers (33 of 33) address name description (continued) page number
registers 28529-dsh-001-k mindspeed technologies ? 151 mindspeed proprietary and confidential 2.2.2 0x01?ensumint (summary interrupt control register) the ensumint register controls which of the interrupts listed in the sumint register (0x00) appear in the sumport register and on the microint* (pin aa1), prov ided the corresponding ensumport bit is enabled and enintpin (bit 3) in the genctrl register (0xf00) is enabled. bit default name description 7 0 ? reserved, set to a logical 0. 6 0 ? reserved, set to a logical 0. 5 0 ? reserved, set to a logical 0. 4 0 ? reserved, set to a logical 0. 3 0 ? reserved, set to a logical 0. 2 0 ? reserved, set to a logical 0. 1 0 entxcellint when written to a logical 1, this bit enab les the transmit cell interrupts located in the txcellint register (0x2c). these interrupts appear can on the microint* pin (pin aa1), provided that enportint in the ensumport0-3 re gister (0x0f06, 0x0f08, 0x0f0a, 0x0f0c) is enabled for this port and enintpin (bit 3) in the genc trl register (0x0f00) is enabled. 0 0 enrxcellint when written to a logical 1, this bit enables the receive cell interrupts located in the rxcellint register (0x2d). these interrupts can appear on the microint* pin (pin aa1), provided that enportint in the ensumport0-3 re gister (0x0f06, 0x0f08, 0x0f0a, 0x0f0c) is enabled for this port and enintpin (bit 3) in the genc trl register (0x0f00) is enabled.
registers 28529-dsh-001-k mindspeed technologies ? 152 mindspeed proprietary and confidential 2.2.3 0x04?pmode (port mode control register) the pmode register controls the port-level software resets, source loopback, and physical layer interface mode. bit default name description 7 0 prtmstrst when written to a logical 1, this bit init iates a port master reset. all internal state machines associated with this port are r eset and all control re gisters for this port, except this one, assume their default values. only bits 0?6 in this re gister are overwritten wi th their default values. 6 0 prtlgcrst when written to a logical 1, this bit init iates a port logic reset. al l internal state machines associated with this port are reset but all regi sters (0x00?0x3f) listed as ?type: w/r? in table 2- 3 are unaltered. output signals for this port are three-state dur ing port logic reset. 5 0 srcloop (1) when written to a logical 1, this bit enables a source loopback. the line transmit clock and data outputs are connected to the line receive clock and data inputs. refer to figure 1-12 . during source loopback mode 0, the device is automatically configured for general purpose mode (ignoring the contents of the phytype[2:0] bits). 4 0 felnloop (1) enables far-end line loopback. in this mode, the receive data is processed by the tc block and looped back at the utopia interface to the transmit side. refer to figure 1-13 . 3 0 srcloopmode (1) when source loopback is enabled (when srcloop is written to a logic 1), this bit select between the two types of source loopback as follows: 0 - source loopback 0 selected 1 - source loopback 1 selected 2 0 phytype[2] (1) these bits determine the physical layer interface mode: in general purpose mode, th e sprxsync and sptxsync pi ns are ignored. (however, good design practice would have them tied high.) 1 0 phytype[1] (1) 0 0 phytype[0] (1) footnote: (1) these bits should only be changed when the device or port logic reset is asserted. 000?t1 mode 011?reserved 110?dsl mode 001?e1 mode 100?reserved 111?power down 010?reserved 101?general purpose
registers 28529-dsh-001-k mindspeed technologies ? 153 mindspeed proprietary and confidential 2.2.4 0x05?iomode (input/output mode control register) the iomode register controls the line interf ace signal polarities and status outputs. bit default name description 7 0 ? reserved, set to 0. 6 0 rxsyncpol (1) this bit determines the receiver sy nchronization input polarity. when written to a logical 1, the active level on the sprxsync input is high. when written to a logical 0, the active level is low. 50rxclkpol (1) this bit determines the receiver clock input polarity . when written to a logical 1, the active edge on the sprxclk input is the falling edge. when written to a logical 0, the active edge is the rising edge. 40txsyncpol (1) this bit determines the transmitter synchronization input polarity. when written to a logical 1, the active level on the sptxsync input is high. when written to a logical 0, the active level is low. 30txclkpol (1) this bit determines the transmitter clock input polarity. when written to a logical 1, the active edge on the sptxclk input is the falling edge. when written to a logical 0, the active edge is the rising edge. 20txdatshft (1) this bit when set to a logical 1 shifts the serial tx data by 1/2 a cycle. this results in the tx data being output a 1/2 sptxclk cycle later than when the tx inputs are sampled. this feature is disabled when set to 0. 1 0 ? reserved, set to 0. 0 0 ? reserved, set to 0. footnote: (1) these bits should only be changed when the device or port logic reset is asserted.
registers 28529-dsh-001-k mindspeed technologies ? 154 mindspeed proprietary and confidential 2.2.5 0x08?cgen (cell gene ration control register) the cgen register controls the device?s cell generation functions. bit default name description 7 0 dishec when written to a logical 1, this bit disables internal generation of the hec field. when disabled, the hec field from the utopia interface rema ins unchanged in the transmitted cell. when written to a logical 0, hec is internally ca lculated and inserted in the transmitted cell. 6 1 entxcos when written to a logical 1, this bit enables the transmit hec coset. when written to a logical 0, the hec coset is disabled. 5 1 entxcellscr when written to a logical 1, this bit en ables the transmit cell scrambler. when written to a logical 0, the transmit cell scrambler is disabled. 4 0 errhec when written to a logical 1, this bit causes the errpat register to be xored with the calculated hec byte for one transmit cell. th ese bits are cleared automatically by internal circuitry after the indicated error insertion has t aken place. clearing takes preceden ce over a simultaneous write operation to this register. 3 0 dslsyncpol this bit controls the polarity of the sync pulse in dsl mode. set to 1 for active high and to 0 for active low. 2 0 ? reserved, write to a logical 0. 1 0 entxdssscr when written to a logical 1, this bit enab les the transmit dss scrambler. when written to a logical 0, the transmit d ss scrambler is disabled. 0 0 enrxdssscr when written to a logical 1, this bit enables the receive dss scrambler. when written to a logical 0, the receive dss scrambler is disabled.
registers 28529-dsh-001-k mindspeed technologies ? 155 mindspeed proprietary and confidential 2.2.6 0x09?hdrfield (header field control register) the hdrfield register controls the header insertion elements. 2.2.7 0x0a?idlpay (transmit idle cell payload control register) the idlpay register contains the transmit idle cell payload. bit default name description 7 0 ? reserved, write to a logical 0. 6 0 ? reserved, write to a logical 0. 5 0 ? reserved, write to a logical 0. 4 0 insgfc when written to a logical 1, this bit inserts a generic flow control (gfc) field in the outgoing header from the txhdr registers. when written to a logical 0, the gfc field is not changed prior to transmission. 3 0 insvpi when written to a logical 1, this bit inserts a virtual path identifier (vpi) field in the outgoing header from the txhdr registers. when written to a logical 0, the vpi field is not changed prior to transmission. 2 0 insvci when written to a logical 1, this bit inserts a virtual channel identifier (vci) field in the outgoing header from the txhdr registers. when written to a logical 0, the vci field is not changed prior to transmission. 1 0 inspt when written to a logical 1, this bit inserts a payload type (pt) field in the outgoing header from the txhdr registers. when written to a logical 0, the pt field is not changed prior to transmission. 0 0 insclp when written to a logical 1, this bit inserts a cell loss priority (clp) bit in the outgoing header from the txhdr registers. when written to a lo gical 0, the clp field is not changed prior to transmission. bit default name description 7 0 idlpay[7] these bits hold the transmit idle cell payload values for outgoing idle cells. 6 1 idlpay[6] 5 1 idlpay[5] 4 0 idlpay[4] 3 1 idlpay[3] 2 0 idlpay[2] 1 1 idlpay[1] 0 0 idlpay[0]
registers 28529-dsh-001-k mindspeed technologies ? 156 mindspeed proprietary and confidential 2.2.8 0x0b?errpat (error pattern control register) the errpat register provides the error pattern for the hec error insertion function. errhec (bit 4) in the cgen register (0x08) enables this function. each bit in the error pattern register is xored with the corresponding bit of the calculated hec byte to be errored. 2.2.9 0x0c?cval (cell validation control register) the cval register controls th e validation of incoming cells. bit default name description 7 0 errpat[7] error pattern bit 7. 6 0 errpat[6] error pattern bit 6. 5 0 errpat[5] error pattern bit 5. 4 0 errpat[4] error pattern bit 4. 3 0 errpat[3] error pattern bit 3. 2 0 errpat[2] error pattern bit 2. 1 0 errpat[1] error pattern bit 1. 0 0 errpat[0] error pattern bit 0. bit default name description 7 0 rejhdr when written to a logical 1, this bit enables the rejection of certain header cells. when enabled, cells with headers matching the rxhdrx/rxmskx definition are rejected and all others are accepted. when written to a logical 0, cells wi th matching headers are accepted and cells with non-matching header s are rejected. 6 1 delidle when written to a logical 1, this bit enable s the deletion of idle cells. when enabled, cells matching the rxidl/idlmsk defi nition are deleted from the recei ved cell stream. when written to a logical 0, idle cells are included in the received stream. 5 1 enrxcos when written to a logical 1, this bit enable s the receive hec coset. when written to a logical 0, the hec coset is disabled. 4 1 enrxcellscr when written to a logical 1, this bit enable s the receive cell scrambler. when written to a logical 0, the receive cell scrambler is disabled. 3 0 enheccorr when written to a logical 1, this bit enab les hec correction. when written to a logical 0, hec correction is disabled. 2 0 dishecchk when written to a logical 1, this bit di sables hec checking. when writ ten to a logical 0, hec checking is performed as a ce ll validation criterion. see table 1-26 . 1 0 discellrcvr when written to a logical 1, this bit disables the cell receiver . when disabled, all cell reception is disabled on the next cell boundary. when written to a logical 0, cell reception begins or resumes on the next cell boundary. 0 0 dislocd when written to a logical 1, this bit disabl es loss of cell deli neation. when di sabled, cells are passed even if cell delineation has not been found. when written to a logical 0, cells are passed only while cell alignment has been achieved. see table 1-26 .
registers 28529-dsh-001-k mindspeed technologies ? 157 mindspeed proprietary and confidential 2.2.10 0x0d?utop1 (utopia control register 1) the utop1 register controls the utopia resets. 2.2.11 0x0e?utop2 (utopia cont rol register 2) (tc block) the utop2 register contains the multi-phy address value for the port. bit default name description 7 0 txreset when written to a logical 1, this bit resets the transmit fifo pointers. this reset should only be used as a test function becau se it can create short cells. 6 0 rxreset when written to a logical 1, this bit resets the receive fifo pointers. this reset should only be used as a test function becau se it can create short cells. 5 0 ? reserved, write to a logical 0. 4 0 ? reserved, write to a logical 0. 3 0 ? reserved, write to a logical 0. 2 0 ? reserved, write to a logical 0. 1 0 ? reserved, write to a logical 0. 0 0 ? reserved, write to a logical 0. bit default name description 7 0 ? reserved, write to a logical 0. 6 0 ? reserved, write to a logical 0. 51utopdis (1) when written to a logical 1, this bit disables utopia outputs for this port. 4 0 mphyaddr[4]?msb (1) these bits are the multi-phy device address. each m2852x port should have a unique address. these bits correspond to the urxaddr and utxaddr pins. when the pin ma tches the bit values, the port is accessed. this port ignores any transact ions meant for another port or phy device. 3 (2) mphyaddr[3] (1) 2 (2) mphyaddr[2] (1) 1 (2) mphyaddr[1] (1) 0 (2) mphyaddr[0]?lsb (1) footnote: (1) these bits should only be changed when the device or port logic reset is asserted. (2) the default for these bits is the po rt number for each port. (0000?port 0, 00 01?port 1, 0010?port 2, 0011?port 3, 0100?port 4, 0101?port 5, 0110?port 6, 0111?port 7, 1000?port 8, 1001?po rt 9, 1010?port 10, 1011?port 11, 1100?port 12, 1101?port 13, 1110?port 14, 1111?port 15, 0000?port 16, 0001?port 17, 0010?port 18, 0011?port 19, 0100?port 20, 0101?port 21, 0110?port 22, 0111?port 23, 1000?port 24, 1001?port 25, 1010? port 26, 1011?port 27, 1100?port 28, 1101?port 29, 1110?port 30, 1111?port 31)
registers 28529-dsh-001-k mindspeed technologies ? 158 mindspeed proprietary and confidential 2.2.12 0x0f?udf2 (udf 2 control register) the contents of the udf2 register are inserted into the udf2 byte on the utopia receive bus when operating in 16-bit utopia mode. 2.2.13 0x10?txhdr1 (transmit ce ll header control register 1) the txhdr1 register contains the first byte of the transmit cell header. it controls the header value that is inserted in the transmitted cell. this header consists of 32 bits divided among four registers (txhdr1?4). bit default name description 7 0 udf2[7] the contents of this register are output o ver the utopia receive bus when operating in utopia 16-bit mode. the default matches the port address. 60udf2[6] 50udf2[5] 40udf2[4] 3(1)udf2[3] 2(1)udf2[2] 1(1)udf2[1] 0(1)udf2[0] footnote: (1) the default for these bits is the po rt number for each port. (0000?port 0, 00 01?port 1, 0010?port 2, 0011?port 3, 0100?port 4, 0101?port 5, 0110?port 6, 0111?port 7, 1000?port 8, 1001?po rt 9, 1010?port 10, 1011?port 11, 1100?port 12, 1101?port 13, 1110?port 14, 1111?port 15, 0000?port 16, 0001?port 17, 0010?port 18, 0011?port 19, 0100?port 20, 0101?port 21, 0110?port 22, 0111?port 23, 1000?port 24, 1001?port 25, 1010? port 26, 1011?port 27, 1100?port 28, 1101?port 29, 1110?port 30, 1111?port 31) bit default name description 7 0 txhdr1[7] these bits hold the transmit header values fo r octet 1 of the outgoing cell. insertion of the bits is controlled by the hdrfield register (0x09). gfc/vpi bits (for uni they are gfc bits, for nni they are vpi bits) 6 0 txhdr1[6] 5 0 txhdr1[5] 4 0 txhdr1[4] 3 0 txhdr1[3] vpi bits 2 0 txhdr1[2] 1 0 txhdr1[1] 0 0 txhdr1[0]
registers 28529-dsh-001-k mindspeed technologies ? 159 mindspeed proprietary and confidential 2.2.14 0x11?txhdr2 (transmit ce ll header control register 2) the txhdr2 register contains the second byte of the transmit cell header. (see 0x10?txhdr1.) 2.2.15 0x12?txhdr3 (transmit ce ll header control register 3) the txhdr3 register contains the third byte of the transmit cell header. (see 0x10?txhdr1.) bit default name description 7 0 txhdr2[7] these bits hold the transmit header values fo r octet 2 of the outgoing cell. insertion of the bits is controlled by the hdrfield register (0x09). vpi bits 6 0 txhdr2[6] 5 0 txhdr2[5] 4 0 txhdr2[4] 3 0 txhdr2[3] vci bits 2 0 txhdr2[2] 1 0 txhdr2[1] 0 0 txhdr2[0] bit default name description 7 0 txhdr3[7] these bits hold the transmit header values fo r octet 3 of the outgoing cell. insertion of the bits is controlled by the hdrfield register (0x09). vci bits 6 0 txhdr3[6] 5 0 txhdr3[5] 4 0 txhdr3[4] 3 0 txhdr3[3] 2 0 txhdr3[2] 1 0 txhdr3[1] 0 0 txhdr3[0]
registers 28529-dsh-001-k mindspeed technologies ? 160 mindspeed proprietary and confidential 2.2.16 0x13?txhdr4 (transmit ce ll header control register 4) the txhdr4 register contains the fourth byte of the transmit cell header. (see 0x10?txhdr1.) 2.2.17 0x14?txidl1 (transmit idle cell header control register 1) the txidl1 register contains the first byte of the transmit idle cell header. it controls the header value that is inserted in the transmitted idle cells. this header consists of 32 bits divided among four registers. bit default name description 7 0 txhdr4[7] these bits hold the transmit header values fo r octet 4 of the outgoing cell. insertion of the bits is controlled by the hdrfield register (0x09). vci bits 6 0 txhdr4[6] 5 0 txhdr4[5] 4 0 txhdr4[4] 3 0 txhdr4[3] payload-type bits 2 0 txhdr4[2] 1 0 txhdr4[1] 0 0 txhdr4[0] cell loss priority bit bit default name description 7 0 txidl1[7] these bits hold the transmit idle cell header values for octet 1 of the outgoing cell. gfc/vpi bits (for uni they are gfc bits, for nni the are vpi bits) 60txidl1[6] 50txidl1[5] 40txidl1[4] 30txidl1[3] vpi bits 20txidl1[2] 10txidl1[1] 00txidl1[0]
registers 28529-dsh-001-k mindspeed technologies ? 161 mindspeed proprietary and confidential 2.2.18 0x15?txidl2 (transmit idle cell header control register 2) the txidl2 register contains the second byte of the transmit idle cell header. (see 0x14?txidl1.) 2.2.19 0x16?txidl3 (transmit idle cell header control register 3) the txidl3 register contains the third byte of the transmit idle cell header. (see 0x14?txidl1.) bit default name description 7 0 txidl2[7] these bits hold the transmit idle cell header values for octet 2 of the outgoing cell. vpi bits 60txidl2[6] 50txidl2[5] 40txidl2[4] 30txidl2[3] vci bits 20txidl2[2] 10txidl2[1] 00txidl2[0] bit default name description 7 0 txidl3[7] these bits hold the transmit idle cell header values for octet 3 of the outgoing cell. vci bits 60txidl3[6] 50txidl3[5] 40txidl3[4] 30txidl3[3] 20txidl3[2] 10txidl3[1] 00txidl3[0]
registers 28529-dsh-001-k mindspeed technologies ? 162 mindspeed proprietary and confidential 2.2.20 0x17?txidl4 (transmit idle cell header control register 4) the txidl4 register contains the fourth byte of the transmit idle cell header. (see 0x14?txidl1.) 2.2.21 0x18?rxhdr1 (receive ce ll header control register 1) the rxhdr1 register contains the first byte of the receive cell header. the header values direct atm cells to the utopia port if an incoming atm cell header matches the value in the header register. receive header mask registers further qualify atm cell reception. this header consists of 32 bits divided among four registers. bit default name description 7 0 txidl4[7] these bits hold the transmit idle cell header values for octet 4 of the outgoing cell. vci bits 60txidl4[6] 50txidl4[5] 40txidl4[4] 30txidl4[3] payload-type bits 20txidl4[2] 10txidl4[1] 01txidl4[0] cell loss priority bit bit default name description 7 0 rxhdr1[7] these bits hold the receive header values for octet 1 of the incoming cell. 6 0 rxhdr1[6] 5 0 rxhdr1[5] 4 0 rxhdr1[4] 3 0 rxhdr1[3] 2 0 rxhdr1[2] 1 0 rxhdr1[1] 0 0 rxhdr1[0]
registers 28529-dsh-001-k mindspeed technologies ? 163 mindspeed proprietary and confidential 2.2.22 0x19?rxhdr2 (receive ce ll header control register 2) the rxhdr2 register contains the second byte of the receive cell he ader. (see 0x18?rxhdr1.) 2.2.23 0x1a?rxhdr3 (receive cell header control register 3) the rxhdr3 register contains the third byte of the receive cell header. (see 0x18?rxhdr1.) bit default name description 7 0 rxhdr2[7] these bits hold the receive header values for octet 2 of the incoming cell. 6 0 rxhdr2[6] 5 0 rxhdr2[5] 4 0 rxhdr2[4] 3 0 rxhdr2[3] 2 0 rxhdr2[2] 1 0 rxhdr2[1] 0 0 rxhdr2[0] bit default name description 7 0 rxhdr3[7] these bits hold the receive header values for octet 3 of the incoming cell. 6 0 rxhdr3[6] 5 0 rxhdr3[5] 4 0 rxhdr3[4] 3 0 rxhdr3[3] 2 0 rxhdr3[2] 1 0 rxhdr3[1] 0 0 rxhdr3[0]
registers 28529-dsh-001-k mindspeed technologies ? 164 mindspeed proprietary and confidential 2.2.24 0x1b?rxhdr4 (receive cell header control register 4) the rxhdr4 register contains the fourth byte of the receive cell header. (see 0x18?rxhdr1.) 2.2.25 0x1c?rxmsk1 (receive ce ll mask control register 1) the rxmsk1 register contains the first byte of the receive cell mask. it modifies atm cell screening, which compares the receive cell header registers to the incoming cells. setting a bit in the mask register causes the corresponding bit in the received atm cell header to be disregarded for screening. for example, setting rxmsk1 bit 0 to 1 causes atm cells to be accepted with either 1 or 0 in the octet 1, bit 0 position. combinations of receive header mask bits can select groups of atm vpi/vcis for re ception. this mask consists of 32 bits divided among four registers. bit default name description 7 0 rxhdr4[7] these bits hold the receive header values for octet 4 of the incoming cell. 6 0 rxhdr4[6] 5 0 rxhdr4[5] 4 0 rxhdr4[4] 3 0 rxhdr4[3] 2 0 rxhdr4[2] 1 0 rxhdr4[1] 0 0 rxhdr4[0] bit default name description 7 1 rxmsk1[7] these bits hold the receive head er mask for octet 1 of the incoming cell. 6 1 rxmsk1[6] 5 1 rxmsk1[5] 4 1 rxmsk1[4] 3 1 rxmsk1[3] 2 1 rxmsk1[2] 1 1 rxmsk1[1] 0 1 rxmsk1[0]
registers 28529-dsh-001-k mindspeed technologies ? 165 mindspeed proprietary and confidential 2.2.26 0x1d?rxmsk2 (receive ce ll mask control register 2) the rxmsk2 register contains the second byte of the receive cell mask. (see 0x1d?rxmsk1.) 2.2.27 0x1e?rxmsk3 (receive ce ll mask control register 3) the rxmsk3 register contains the third byte of the receive cell mask. (see 0x1d?rxmsk1.) bit default name description 7 1 rxmsk2[7] these bits hold the receive head er mask for octet 2 of the incoming cell. 6 1 rxmsk2[6] 5 1 rxmsk2[5] 4 1 rxmsk2[4] 3 1 rxmsk2[3] 2 1 rxmsk2[2] 1 1 rxmsk2[1] 0 1 rxmsk2[0] bit default name description 7 1 rxmsk3[7] these bits hold the receive head er mask for octet 3 of the incoming cell. 6 1 rxmsk3[6] 5 1 rxmsk3[5] 4 1 rxmsk3[4] 3 1 rxmsk3[3] 2 1 rxmsk3[2] 1 1 rxmsk3[1] 0 1 rxmsk3[0]
registers 28529-dsh-001-k mindspeed technologies ? 166 mindspeed proprietary and confidential 2.2.28 0x1f?rxmsk4 (receive ce ll mask control register 4) the rxmsk4 register contains the fourth byte of the receive cell mask. (see 0x1d?rxmsk1.) 2.2.29 0x20?rxidl1 (receive idle cell header control register 1) the rxidl1 register contains the first byte of the receive idle cell header. it defines atm idle cells for the cell receiver. idle cells are discarded from the received stream if register cval (0x0c) bit 6 is set to 1. this header consists of 32 bits divided among four registers. bit default name description 7 1 rxmsk4[7] these bits hold the receive head er mask for octet 4 of the incoming cell. 6 1 rxmsk4[6] 5 1 rxmsk4[5] 4 1 rxmsk4[4] 3 1 rxmsk4[3] 2 1 rxmsk4[2] 1 1 rxmsk4[1] 0 1 rxmsk4[0] bit default name description 7 0 rxidl1[7] these bits hold the receive idle cel l header for octet 1 of the incoming cell. 60rxidl1[6] 50rxidl1[5] 40rxidl1[4] 30rxidl1[3] 20rxidl1[2] 10rxidl1[1] 00rxidl1[0]
registers 28529-dsh-001-k mindspeed technologies ? 167 mindspeed proprietary and confidential 2.2.30 0x21?rxidl2 (receive idle cell header control register 2) the rxidl2 register contains the second byte of the receive idle cell header. (see 0x20?rxidl1.) 2.2.31 0x22?rxidl3 (receive idle cell header control register 3) the rxidl3 register contains the third byte of the receive idle cell header. (see 0x20?rxidl1.) bit default name description 7 0 rxidl2[7] these bits hold the receive idle cel l header for octet 2 of the incoming cell. 60rxidl2[6] 50rxidl2[5] 40rxidl2[4] 30rxidl2[3] 20rxidl2[2] 10rxidl2[1] 00rxidl2[0] bit default name description 7 0 rxidl3[7] these bits hold the receive idle cel l header for octet 3 of the incoming cell. 60rxidl3[6] 50rxidl3[5] 40rxidl3[4] 30rxidl3[3] 20rxidl3[2] 10rxidl3[1] 00rxidl3[0]
registers 28529-dsh-001-k mindspeed technologies ? 168 mindspeed proprietary and confidential 2.2.32 0x23?rxidl4 (receive idle cell header control register 4) the rxidl4 register contains the fourth byte of the receive idle cell header. (see 0x20?rxidl1.) 2.2.33 0x24?idlmsk1 (receive idle cell mask control register 1) the idlmsk1 register contains the first byte of the rece ive idle cell mask. it modifi es atm cell screening, which compares the receive idle cell header registers to the incoming cells. setting a bit in the mask register causes the corresponding bit in the received atm idle cell header to be disregarded for screening. for example, setting idlmsk1 bit 0 to 1 causes cells to be accepted as atm idle cells with either 1 or 0 in the octet 1, bit 0 position. this header consists of 32 bits divided among four registers. bit default name description 7 0 rxidl4[7] these bits hold the receive idle cel l header for octet 4 of the incoming cell. 60rxidl4[6] 50rxidl4[5] 40rxidl4[4] 30rxidl4[3] 20rxidl4[2] 10rxidl4[1] 01rxidl4[0] bit default name description 7 0 idlmsk1[7] these bits hold the receive idle cel l header mask for octet 1 of the incoming cell. 6 0 idlmsk1[6] 5 0 idlmsk1[5] 4 0 idlmsk1[4] 3 0 idlmsk1[3] 2 0 idlmsk1[2] 1 0 idlmsk1[1] 0 0 idlmsk1[0]
registers 28529-dsh-001-k mindspeed technologies ? 169 mindspeed proprietary and confidential 2.2.34 0x25?idlmsk2 (receive idle cell mask control register 2) the idlmsk2 register contains the second byte of the receive idle cell mask. (see 0x24?rxmskl1.) 2.2.35 0x26?idlmsk3 (receive idle cell mask control register 3) the idlmsk3 register contains the third byte of the receive idle cell mask. (see 0x24?rxmskl1.) bit default name description 7 0 idlmsk2[7] these bits hold the receive idle cel l header mask for octet 2 of the incoming cell. 6 0 idlmsk2[6] 5 0 idlmsk2[5] 4 0 idlmsk2[4] 3 0 idlmsk2[3] 2 0 idlmsk2[2] 1 0 idlmsk2[1] 0 0 idlmsk2[0] bit default name description 7 0 idlmsk3[7] these bits hold the receive idle cel l header mask for octet 3 of the incoming cell. 6 0 idlmsk3[6] 5 0 idlmsk3[5] 4 0 idlmsk3[4] 3 0 idlmsk3[3] 2 0 idlmsk3[2] 1 0 idlmsk3[1] 0 0 idlmsk3[0]
registers 28529-dsh-001-k mindspeed technologies ? 170 mindspeed proprietary and confidential 2.2.36 0x27?idlmsk4 (receive idle cell mask control register 4) the idlmsk4 register contains the fourth byte of the receive idle cell mask. (see 0x24?rxmskl1.) 2.2.37 0x28?encellt (transmit ce ll interrupt control register) the encellt register controls which of the interrupts listed in the txcellint register (0x2c) appear on the microint* pin (pin aa1), provided that both entxcellint (bit 1) in the ensumint register (0x01) and enportint bit in the appropriate ensumportn (n= 0 - 3) register (0xf06, 0xf08, 0xf0a or 0xf0c) for this port are enabled, and enintpin (bit 3) in the genctrl register (0xf00) is enabled. bit default name description 7 0 idlmsk4[7] these bits hold the receive idle cel l header mask for octet 4 of the incoming cell. 6 0 idlmsk4[6] 5 0 idlmsk4[5] 4 0 idlmsk4[4] 3 0 idlmsk4[3] 2 0 idlmsk4[2] 1 0 idlmsk4[1] 0 0 idlmsk4[0] bit default name description 7 1 enparerrint when written to a logical 1, th is bit enables the pa rity error interrupt. 6 1 ensocerrint when written to a logical 1, this bit enables the start of cell error interrupt. 5 1 entxovflint when written to a logical 1, this bi t enables the transmit fifo overflow interrupt. 4 1 enrxovflint when written to a logical 1, this bit enables the receive fifo overflow interrupt. 3 1 encellsentint when written to a logical 1, this bit enables the cell sent interrupt. 2 0 ? reserved for factory test, ignore. 1 0 ? reserved, set to a logical 0. 0 0 ? reserved, set to a logical 0.
registers 28529-dsh-001-k mindspeed technologies ? 171 mindspeed proprietary and confidential 2.2.38 0x29?encellr (receive ce ll interrupt control register) the encellr register controls which of the interrupts listed in the rxcellint register (0x2d) appear on the microint* pin (pin aa1), provided that both enrxcellint (bit 0) in the ensumint register (0x01) and enportint bit in the appropriate ensumportn (n= 0 - 3) register (0xf06, 0xf08, 0xf0a or 0xf0c) for this port are enabled, and enintpin (bit 3) in the genctrl register (0xf00) is enabled. 2.2.39 0x2c?txcellint (transmit cell in terrupt indication status register) the txcellint register indicates that a change of status has occurred within the transmit status signals. bit default name description 7 1 enlocdint when written to a logical 1, this bi t enables a loss of cell delineation interrupt. 6 1 enhecdetint when written to a logical 1, this bit enables a hec error detected interrupt. 5 1 enheccorrint when written to a logical 1, th is bit enables a hec error corrected interrupt. 4 1 ? reserved, write to a logical 0. 3 1 encellrcvdint when written to a logical 1, this bit enables a cell received interrupt. 2 1 enidlercvdint when written to a logical 1, th is bit enables an idle cell received interrupt. 1 1 ennonmatchint when written to a logical 1, this bit enables a non-matching cell received interrupt. 0 1 ennonzergfcint when written to a logical 1, this bit enables a non-zero gfc received interrupt. bit default name description 7 ? parerrint (1) when a logical 1 is read, this bit indicates that a parity error occurred. 6 ? socerrint (1) when a logical 1 is read, this bit indica tes that a start of cell error occurred. 5 ? txovflint (1) when a logical 1 is read, this bit indicat es that a transmit fifo overflow occurred. 4?rxovflint (1) when a logical 1 is read, this bit indica tes that a receive fi fo overflow occurred. 3 ? cellsentint (1) when a logical 1 is read, this bit indicates that a cell has been sent. 2 ? ? reserved for factory test, ignore. 1 0 ? reserved, set to a logical 0. 0 0 ? reserved, write to a logical 0. footnote: (1) single event?a 0 to 1 transition on the co rresponding status bit causes this interrupt to occur, provided that this interrup t has been enabled by the corresponding enable bit. reading this interrupt re gister clears this interrupt.
registers 28529-dsh-001-k mindspeed technologies ? 172 mindspeed proprietary and confidential 2.2.40 0x2d?rxcellint (receive cell interrupt indication status register) the rxcellint register indicates that a change of status has occurred within the receive status signals. 2.2.41 0x2e?txcell (transm it cell status register) the txcell register contains status for the cell transmit ter. this register is cleared on read. bits 1-7 are read- only . bit default name description 7?locdint (2) when a logical 1 is read, this bit indicates that a loss of cell de lineation has occurred. 6?hecdetint (1) when a logical 1 is read, this bit i ndicates that a hec error was detected. 5 ? heccorrint (1) when a logical 1 is read, this bit indicates that a hec error was corrected. 4 ? ? reserved, write to a logical 0. 3 ? cellrcvdint (1) when a logical 1 is read, this bit i ndicates that a cell has been received. 2 ? idlercvdint (1) when a logical 1 is read, this bit indica tes that an idle cell has been received. 1 ? nonmatchint (1) when a logical 1 is read, this bit indicat es that a non-matching cell has been received. 0 ? nonzergfcint (1) when a logic 1 is read, this bit indicat es that a non-zero gfc has been received. footnote: (1) single event?a 0 to 1 transition on the co rresponding status bit causes this interrupt to occur, provided that this interrup t has been enabled by the corresponding enable bit. reading this interrupt re gister clears this interrupt. (2) dual event?either a 0 to 1 or a 1 to 0 transition on the corre sponding status bit causes this in terrupt to occur, provided t hat this interrupt has been enabled by the corresponding enable bit. reading this interrupt register clears this interrupt. bit default name description 7 ? parerr (1) when a logical 1 is read, this bit indicates th at a parity error was received on the transmit utopia input data octet. 6?socerr (1) when a logical 1 is read, this bi t indicates that a start of cell error was received on the utxsoc pin (pin tbd). 5?txovfl (1) when a logical 1 is read, this bit indicates that a transmit fifo overfl ow condition occurred in the transmit utopia fifo. 4?rxovfl (1) when a logical 1 is read, this bit indicates that a receive fifo overflow condition occurred in the receive utopia fifo. 3?cellsent (1) when a logical 1 is read, this bit indicates th at a non-idle cell was formatted and transmitted. 2 ? ? reserved for factory test, ignore. 1 0 ? reserved, set to a logical 0. 0 0 ? reserved, set to a logical 0. footnote: (1) this status indicates an event that occurred since the register was last read.
registers 28529-dsh-001-k mindspeed technologies ? 173 mindspeed proprietary and confidential 2.2.42 0x2f?rxcell (receive cell status register) the rxcell register contains status for the cell receiver. this register is cleared on read. 2.2.43 0x30?idlcntl (idle cell receive counter [low byte]) the idlcntl counter tracks the number of received idle cells. this byte of the counter should be read first. the counter is cleared on read. bit default name description 7?locd (2) when a logical 1 is read, this bit indicates a loss of cell delineation. 6?hecdet (1) when a logical 1 is read, this bit indicates that an uncorrected hec error was detected. 5 ? heccorr (1) when a logical 1 is read, this bit i ndicates that a hec error was corrected. 4 ? ? reserved, ignore this bit. 3 ? cellrcvd when logical 1 is read, this bi t indicates that a valid cell was received. 2 ? idlercvd (1) when a logical 1 is read, this bit indicates that a cell with a header matching the receive idle cell header value and mask criteria was received. 1 ? nonmatch (1) when a logical 1 is read, this bit indicates that a cell has been rejected by the cell screening function. 0 ? nonzergfc (1) when a logical 1 is read, this bi t indicates that a cell with a non-zero gfc field in the header was received. footnote: (1) this status indicates an event that occurred since the register was last read. (2) this status reflects the current state of the circuit. bit default name description 7 ? idlecnt[7] received cell counter bit 7. 6 ? idlecnt[6] received cell counter bit 6. 5 ? idlecnt[5] received cell counter bit 5. 4 ? idlecnt[4] received cell counter bit 4. 3 ? idlecnt[3] received cell counter bit 3. 2 ? idlecnt[2] received cell counter bit 2. 1 ? idlecnt[1] received cell counter bit 1. 0 ? idlecnt[0] received cell counter bit 0 (lsb).
registers 28529-dsh-001-k mindspeed technologies ? 174 mindspeed proprietary and confidential 2.2.44 0x31?idlcnth (idle cell receive counter [high byte]) the idlcnth counter tracks the number of received cells. the counter is cleared on read. 2.2.45 0x33?locdcnt (locd event counter) this counter tracks the number of times that cell delineation was lost. note that the locd interrupt is a dual event interrupt and is set when cell delineatio n is lost or regained. thus the numb er of locd events will not match the number of locd interrupts. bit default name description 7 ? idlecnt[15] received cell counter bit 15. 6 ? idlecnt[14] received cell counter bit 14. 5 ? idlecnt[13] received cell counter bit 13. 4 ? idlecnt[12] received cell counter bit 12. 3 ? idlecnt[11] received cell counter bit 11. 2 ? idlecnt[10] received cell counter bit 10. 1 ? idlecnt[9] received cell counter bit 9. 0 ? idlecnt[8] received cell counter bit 8. bit default name description 7 ? locdcnt[7] locd event counter bit 7 (msb). 6 ? locdcnt[6] locd event counter bit 6. 5 ? locdcnt[5] locd event counter bit 5. 4 ? locdcnt[4] locd event counter bit 4. 3 ? locdcnt[3] locd event counter bit 3. 2 ? locdcnt[2] locd event counter bit 2. 1 ? locdcnt[1] locd event counter bit 1. 0 ? locdcnt[0] locd event counter bit 0 (lsb).
registers 28529-dsh-001-k mindspeed technologies ? 175 mindspeed proprietary and confidential 2.2.46 0x34?txcntl (transmitte d cell counter [low byte]) the txcntl counter tracks the number of transmitted cells. this byte of the counter should be read first. the counter is cleared on read. 2.2.47 0x35?txcnth (transmitte d cell counter [high byte]) the txcnth counter tracks the number of transmitted cells. the counter is cleared on read. bit default name description 7 ? txcnt[7] transmitted cell counter bit 7. 6 ? txcnt[6] transmitted cell counter bit 6. 5 ? txcnt[5] transmitted cell counter bit 5. 4 ? txcnt[4] transmitted cell counter bit 4. 3 ? txcnt[3] transmitted cell counter bit 3. 2 ? txcnt[2] transmitted cell counter bit 2. 1 ? txcnt[1] transmitted cell counter bit 1. 0 ? txcnt[0] transmitted cell counter bit 0 (lsb). bit default name description 7 ? txcnt[15] transmitted cell counter bit 15. 6 ? txcnt[14] transmitted cell counter bit 14. 5 ? txcnt[13] transmitted cell counter bit 13. 4 ? txcnt[12] transmitted cell counter bit 12. 3 ? txcnt[11] transmitted cell counter bit 11. 2 ? txcnt[10] transmitted cell counter bit 10. 1 ? txcnt[9] transmitted cell counter bit 9. 0 ? txcnt[8] transmitted cell counter bit 8.
registers 28529-dsh-001-k mindspeed technologies ? 176 mindspeed proprietary and confidential 2.2.48 0x37?corrcnt (corre cted hec error counter) the corrcnt counter tracks the number of corrected hec errors. the counter is cleared on read 0x38? rxcntl (received cell counter [low byte]). 2.2.49 0x38?rxcntl (receive d cell counter [low byte]) the rxcntl counter tracks the number of received cells. this byte of the counter should be read first. the counter is cleared on read. bit default name description 7 ? corrcnt[7] corrected hec error counter bit 7 (msb). 6 ? corrcnt[6] corrected hec error counter bit 6. 5 ? corrcnt[5] corrected hec error counter bit 5. 4 ? corrcnt[4] corrected hec error counter bit 4. 3 ? corrcnt[3] corrected hec error counter bit 3. 2 ? corrcnt[2] corrected hec error counter bit 2. 1 ? corrcnt[1] corrected hec error counter bit 1. 0 ? corrcnt[0] corrected hec error counter bit 0 (lsb). bit default name description 7 ? rxcnt[7] received cell counter bit 7. 6 ? rxcnt[6] received cell counter bit 6. 5 ? rxcnt[5] received cell counter bit 5. 4 ? rxcnt[4] received cell counter bit 4. 3 ? rxcnt[3] received cell counter bit 3. 2 ? rxcnt[2] received cell counter bit 2. 1 ? rxcnt[1] received cell counter bit 1. 0 ? rxcnt[0] received cell counter bit 0 (lsb).
registers 28529-dsh-001-k mindspeed technologies ? 177 mindspeed proprietary and confidential 2.2.50 0x39?rxcnth (receiv ed cell counter [high byte]) the rxcnth register tracks the number of received cells. the counter is cleared on read. 2.2.51 0x3b?unccnt (uncor rected hec error counter) the unccnt counter tracks the numb er of uncorrected hec errors. the counter is cleared on read. bit default name description 7 ? rxcnt[15] received cell counter bit 15. 6 ? rxcnt[14] received cell counter bit 14. 5 ? rxcnt[13] received cell counter bit 13. 4 ? rxcnt[12] received cell counter bit 12. 3 ? rxcnt[11] received cell counter bit 11. 2 ? rxcnt[10] received cell counter bit 10. 1 ? rxcnt[9] received cell counter bit 9. 0 ? rxcnt[8] received cell counter bit 8. bit default name description 7 ? unccnt[7] uncorrected hec error counter bit 7 (msb). 6 ? unccnt[6] uncorrected hec error counter bit 6. 5 ? unccnt[5] uncorrected hec error counter bit 5. 4 ? unccnt[4] uncorrected hec error counter bit 4. 3 ? unccnt[3] uncorrected hec error counter bit 3. 2 ? unccnt[2] uncorrected hec error counter bit 2. 1 ? unccnt[1] uncorrected hec error counter bit 1. 0 ? unccnt[0] uncorrected hec error counter bit 0 (lsb).
registers 28529-dsh-001-k mindspeed technologies ? 178 mindspeed proprietary and confidential 2.2.52 0x3c?noncntl (non-match ing cell counter [low byte]) the noncntl counter tracks the number of non-matching cells. this byte of the counter should be read first. the counter is cleared on read. 2.2.53 0x3d?noncnth (non-match ing cell counter [high byte]) the noncnth counter tracks the number of non-matching cells. the counter is cleared on read. bit default name description 7 ? noncnt[7] non-matching cell counter bit 7. 6 ? noncnt[6] non-matching cell counter bit 6. 5 ? noncnt[5] non-matching cell counter bit 5. 4 ? noncnt[4] non-matching cell counter bit 4. 3 ? noncnt[3] non-matching cell counter bit 3. 2 ? noncnt[2] non-matching cell counter bit 2. 1 ? noncnt[1] non-matching cell counter bit 1. 0 ? noncnt[0] non-matching cell counter bit 0 (lsb). bit default name description 7 ? noncnt[15] non-matching cell counter bit 15 (msb). 6 ? noncnt[14] non-matching cell counter bit 14. 5 ? noncnt[13] non-matching cell counter bit 13. 4 ? noncnt[12] non-matching cell counter bit 12. 3 ? noncnt[11] non-matching cell counter bit 11. 2 ? noncnt[10] non-matching cell counter bit 10. 1 ? noncnt[9] non-matching cell counter bit 9. 0 ? noncnt[8] non-matching cell counter bit 8.
registers 28529-dsh-001-k mindspeed technologies ? 179 mindspeed proprietary and confidential 2.3 general control registers 2.3.1 0xf00?genctrl (general device control register) 2.3.2 0xf01?partnum (part and version number register) bit default name description 7 0 devmstrst device master reset. when se t high, all internal state machines in the tc block are held in reset and all registers (except this bit) assume their default values. if conf iguring the device for pass-through operation, a minimum delay of 25 us for ima_sysclk of 66 mhz or 33us for ima_sysclk of 50 mhz is required from the rel ease of device reset to the first access of the ima_rx_trans_table register or ima_rx _atm_trans_table register (0x818/0x819). 6 0 devlgcrst device logic reset. when set high, all internal state machines in the tc block are held in reset but register valu es are unaffected. 5 0 enstatlat when set to 1, the one-second status latching is enabled. the value of the status bits are the events which occurred between the last two one-second events. any events occurring after the last one-second event is not reflected when th e status register is read. those events are reflected in the status register upon the next one -second event. when a status register is read, the status is cleared and is not upd ated until the next one-second event. when set to 0, the one-second status latching is disabled. the value of a status register is the events occurred since the last read of the status register. 4 0 encntrlat when set to 1, the one-second counter latching is enabled. the value of the counter is the number of events counted between the last two one-second events. any events occurring after the last one-second event is not reflected when the counter is read. those events are reflected in the counter upon the next one-second event. when a counter is read, the count is cleared and is not updated until the next one-second event. when set to 0, the one-second counter latching is disabled. the value of a counter is the number of events counted since th e last read of the counter. 3 0 enintpin enables the microint* output pin. 2?1 00 ? reserved, set to zero. 0 0 onesecout when set to 1, the onesecio pin is c onfigured as an output. the pin provides a one-second event pulse. the one-second event is generated intern ally of the device. the event occurs after the device has counted 8000 periods of a 8 khz clock. when set to 0, the onesecio pin is configured as an input. the one-second event must be generated externally, by pulsing the onesecio pin for low-high-low. bit default name description 7?4 pppp partnum[3:0] part number controlled by bondout: 16 tc port version - 0101 32 tc port version - 1001 3?0 0000 version[3:0] version number of the device. nu mber starts at ?0000? for the initial version
registers 28529-dsh-001-k mindspeed technologies ? 180 mindspeed proprietary and confidential 2.3.3 0xf02?phyintfc (phy-side interface control register) 2.3.4 0xf03?atmintfc (atm-side interface control register) 2.3.5 0xf04?statout (output status control register) bit default name description 7 0 ? reserved, set to 0. 6 ? phyintselpin this bit reflec ts the level of the externa l phyintfcsel pin (read only) 5 1 phybuswidth when set to 0, the phy-side utopia interface is set to 16-bit mode. when set to 1, the phy-side utopia interface is set to 8-bit mode. 4?0 00000 ? reserved, set to zero. bit default name description 7?6 00 atmmux[1:0] controls the atm-side utopia interface mux. 00 ? external interface is placed in tr istate mode. 01 ? utopia level 2 interface to ima32 bloc k is enabled. 10 ? utopia level 2 interfac e to tc block is enabled. 11 ? external interface is placed in tr istate mode. 5 0 atmbuswidth when set to 0, the 16-bit utopia bus is enabled when set to 1, the 8-bit utopia bus is enabled. 4 0 dualclavenb when set to 1, dual clav/enb mode on th e interface is enabled. when set to 0, single clav/enb is enabled. for single clav mode, urxenb[1] and utxenb[1] are not used but must be pulled up. 3-0 0000 ? reserved, set to zero. bit default name description 7?2 000000 ? reserved, set to zero. 1?0 00 statout[1:0] the value written into these bits will be asser ted on the statout[1:0] output pins.
registers 28529-dsh-001-k mindspeed technologies ? 181 mindspeed proprietary and confidential 2.3.6 0xf05?sumport0 (summa ry port interrupt status register for tc ports 0-7) 2.3.7 0xf06?ensumport0 (summary port interrupt control register for tc ports 0-7) bit default name description 70portint[7] 1 this bit is a summary indicator of the interrup ts from the port 7 sumint register (0x1c0). 60portint[6] 1 this bit is a summary indicator of the interrupts from the port 6 sumint register (0x180). 50portint[5] 1 this bit is a summary indicator of the interrupts from the port 5 sumint register (0x140). 40portint[4] 1 this bit is a summary indicator of the interrupts from the port 4 sumint register (0x100). 30portint[3] 1 this bit is a summary indicator of the interrup ts from the port 3 sumint register (0x0c0). 20portint[2] 1 this bit is a summary indicator of the interrupts from the port 2 sumint register (0x080). 10portint[1] 1 this bit is a summary indicator of the interrupts from the port 1 sumint register (0x040). 00portint[0] 1 this bit is a summary indicator of the interrupts from the port 0 sumint register (0x000). footnote: (1) this bit is a pointer to the next interru pt indication register to be read. this bit will be cl eared when the interrupt bit in the corresponding interrupt indication register is read and automatically cleared. bit default name description 7 1 enportint[7] when set, this bit enables po rtint[7] to appear on the microint* output. 6 1 enportint[6] when set, this bit enables po rtint[6] to appear on the microint* output. 5 1 enportint[5] when set, this bit enables po rtint[5] to appear on the microint* output. 4 1 enportint[4] when set, this bit enables po rtint[4] to appear on the microint* output. 3 1 enportint[3] when set, this bit enables po rtint[3] to appear on the microint* output. 2 1 enportint[2] when set, this bit enables po rtint[2] to appear on the microint* output. 1 1 enportint[1] when set, this bit enables po rtint[1] to appear on the microint* output. 0 1 enportint[0] when set, this bit enables po rtint[0] to appear on the microint* output.
registers 28529-dsh-001-k mindspeed technologies ? 182 mindspeed proprietary and confidential 2.3.8 0xf07?sumport1 (summa ry port interrupt status register for tc ports 8-15) 2.3.9 0xf08?ensumport1 (summary port interrupt control register for tc ports 8-15) bit default name description 7 0 portint[15] 1 this bit is a summary indicator of the interrupt s from the port 15 sumint register (0x3c0). 6 0 portint[14] 1 this bit is a summary indicator of the interrupt s from the port 14 sumint register (0x380). 5 0 portint[13] 1 this bit is a summary indicator of the interrupt s from the port 13 sumint register (0x340). 4 0 portint[12] 1 this bit is a summary indicator of the interrupt s from the port 12 sumint register (0x300). 3 0 portint[11] 1 this bit is a summary indicator of the interrupt s from the port 11 sumint register (0x2c0). 2 0 portint[10] 1 this bit is a summary indicator of the interrupt s from the port 10 sumint register (0x280). 1 0 portint[9] 1 this bit is a summary indicator of the interrupt s from the port 9 sumint register (0x240). 0 0 portint[8] 1 this bit is a summary indicator of the interrupt s from the port 8 sumint register (0x200). footnote: (1) this bit is a pointer to the next interrupt indication regist er to be read. this bit will be cleared when the interrupt bit in the corresponding interrupt indication register is read and automatically cleared. bit default name description 7 1 enportint[15] when set, this bit enables po rtint[15] to appear on the microint* output. 6 1 enportint[14] when set, this bit enables po rtint[14] to appear on the microint* output. 5 1 enportint[13] when set, this bit enables po rtint[13] to appear on the microint* output. 4 1 enportint[12] when set, this bit enables po rtint[12] to appear on the microint* output. 3 1 enportint[11] when set, this bit enables po rtint[11] to appear on the microint* output. 2 1 enportint[10] when set, this bit enables po rtint[10] to appear on the microint* output. 1 1 enportint[9] when set, this bit enables po rtint[9] to appear on the microint* output. 0 1 enportint[8] when set, this bit enables po rtint[8] to appear on the microint* output.
registers 28529-dsh-001-k mindspeed technologies ? 183 mindspeed proprietary and confidential 2.3.10 0xf09?sumport2 (summary port in terrupt status register for tc ports 16-23) 2.3.11 0xf0a?ensumport2 (s ummary port interrupt co ntrol register for tc ports 16-23) bit default name description 7 0 portint[23] 1 this bit is a summary indicator of the interrupt s from the port 23 sumint register (0x5c0). 6 0 portint[22] 1 this bit is a summary indicator of the interrupt s from the port 22 sumint register (0x580). 5 0 portint[21] 1 this bit is a summary indicator of the interrupt s from the port 21 sumint register (0x540). 4 0 portint[20] 1 this bit is a summary indicator of the interrupt s from the port 20 sumint register (0x500). 3 0 portint[19] 1 this bit is a summary indicator of the interrupt s from the port 19 sumint register (0x4c0). 2 0 portint[18] 1 this bit is a summary indicator of the interrupt s from the port 18 sumint register (0x480). 1 0 portint[17] 1 this bit is a summary indicator of the interrupt s from the port 17 sumint register (0x440). 0 0 portint[16] 1 this bit is a summary indicator of the interrupt s from the port 16 sumint register (0x400). footnote: (1) this bit is a pointer to the next interrupt indication regist er to be read. this bit will be cleared when the interrupt bit in the corresponding interrupt indication register is read and automatically cleared. bit default name description 7 1 enportint[23] when set, this bit enables portint[23] to appear on the microint* output. 6 1 enportint[22] when set, this bit enables portint[22] to appear on the microint* output. 5 1 enportint[21] when set, this bit enables portint[21] to appear on the microint* output. 4 1 enportint[20] when set, this bit enables portint[20] to appear on the microint* output. 3 1 enportint[19] when set, this bit enables portint[19] to appear on the microint* output. 2 1 enportint[18] when set, this bit enables portint[18] to appear on the microint* output. 1 1 enportint[17] when set, this bit enables portint[17] to appear on the microint* output. 0 1 enportint[16] when set, this bit enables portint[16] to appear on the microint* output.
registers 28529-dsh-001-k mindspeed technologies ? 184 mindspeed proprietary and confidential 2.3.12 0xf0b?sumport3 (summary port in terrupt status register for tc ports 24-31) 2.3.13 0xf0c?ensumport3 (s ummary port interrupt co ntrol register for tc ports 24-31) 2.3.14 0xf0f?scratch (scratch pad register) bit default name description 7 0 portint[31] 1 this bit is a summary indicator of the interrupt s from the port 31 sumint register (0x7c0). 6 0 portint[30] 1 this bit is a summary indicator of the interrupt s from the port 30 sumint register (0x780). 5 0 portint[29] 1 this bit is a summary indicator of the interrupt s from the port 29 sumint register (0x740). 4 0 portint[28] 1 this bit is a summary indicator of the interrupt s from the port 28 sumint register (0x700). 3 0 portint[27] 1 this bit is a summary indicator of the interrupt s from the port 27 sumint register (0x6c0). 2 0 portint[26] 1 this bit is a summary indicator of the interrupt s from the port 26 sumint register (0x680). 1 0 portint[25] 1 this bit is a summary indicator of the interrupt s from the port 25 sumint register (0x640). 0 0 portint[24] 1 this bit is a summary indicator of the interrupt s from the port 24 sumint register (0x600). footnote: (1) this bit is a pointer to the next interrupt indication regist er to be read. this bit will be cleared when the interrupt bit in the corresponding interrupt indication register is read and automatically cleared. bit default name description 7 1 enportint[31] when set, this bit enables po rtint[31] to appear on the microint* output. 6 1 enportint[30] when set, this bit enables po rtint[30] to appear on the microint* output. 5 1 enportint[29] when set, this bit enables po rtint[29] to appear on the microint* output. 4 1 enportint[28] when set, this bit enables po rtint[28] to appear on the microint* output. 3 1 enportint[27] when set, this bit enables po rtint[27] to appear on the microint* output. 2 1 enportint[26] when set, this bit enables po rtint[26] to appear on the microint* output. 1 1 enportint[25] when set, this bit enables po rtint[25] to appear on the microint* output. 0 1 enportint[24] when set, this bit enables po rtint[24] to appear on the microint* output. bit default name description 7-0 00000000 scratch these bits can be written and read by the system. these bits are not used for any purpose inside the device.
registers 28529-dsh-001-k mindspeed technologies ? 185 mindspeed proprietary and confidential 2.3.15 0xf10?tcctrl0 (tc contro l register for tc ports 0-3) 2.3.16 0xf11?tcctrl1 (tc contro l register for tc ports 4-7) bit default name description 7 0 ihtxdatshft0 when set to 1, the tx data on the interl eaved highway data bus 0 will be output 1/2 ihtxclk0 cycle later than when the tx inputs are sam pled. set to 0 to disable 1/2 cycle shift. 6 0 ihtxclkpol0 interleaved highw ay bus 0 tx clock polarity. set to 0 for rising edge of ihtxclk0, set to 1 for falling edge. 5 0 ihrxclkpol0 interleaved highway bus 0 rx clock polarity. set to 0 for rising edge of ihrxclk0, set to 1 for falling edge. 4 0 enih0 when set, this bit enables interleaved highway interface for tc ports 0-3. 3 0 enfrac[3] when set, this bit enables fractional t1/e1 logic for tc port 3. 2 0 enfrac[2] when set, this bit enables fractional t1/e1 logic for tc port 2. 1 0 enfrac[1] when set, this bit enables fractional t1/e1 logic for tc port 1. 0 0 enfrac[0] when set, this bit enables fractional t1/e1 logic for tc port 0. bit default name description 7 0 ihtxdatshft1 when set to 1, the tx data on the interl eaved highway data bus 1 will be output 1/2 ihtxclk1 cycle later than when the tx inputs are sam pled. set to 0 to disable 1/2 cycle shift. 6 0 ihtxclkpol1 interleaved highw ay bus 1 tx clock polarity. set to 0 for rising edge of ihtxclk1, set to 1 for falling edge. 5 0 ihrxclkpol1 interleaved highway bus 1 rx clock polarity. set to 0 for rising edge of ihrxclk1, set to 1 for falling edge. 4 0 enih1 when set, this bit enables interleaved highway interface for tc ports 4-7. 3 0 enfrac[7] when set, this bit enables fractional t1/e1 logic for tc port 7. 2 0 enfrac[6] when set, this bit enables fractional t1/e1 logic for tc port 6. 1 0 enfrac[5] when set, this bit enables fractional t1/e1 logic for tc port 5. 0 0 enfrac[4] when set, this bit enables fractional t1/e1 logic for tc port 4.
registers 28529-dsh-001-k mindspeed technologies ? 186 mindspeed proprietary and confidential 2.3.17 0xf12?tcctrl2 (tc control register for tc ports 8-11) 2.3.18 0xf13?tcctrl3 (tc control register for tc ports 12-15) bit default name description 7 0 ihtxdatshft2 when set to 1, the tx data on the interl eaved highway data bus 2 will be output 1/2 ihtxclk2 cycle later than when the tx inputs are sam pled. set to 0 to disable 1/2 cycle shift. 6 0 ihtxclkpol2 interleaved highw ay bus 2 tx clock polarity. set to 0 for rising edge of ihtxclk2, set to 1 for falling edge. 5 0 ihrxclkpol2 interleaved highway bus 2 rx clock polarity. set to 0 for rising edge of ihrxclk2, set to 1 for falling edge. 4 0 enih2 when set, this bit enables interleaved highway interface for tc ports 8-11. 3 0 enfrac[11] when set, this bit enables fractional t1/e1 logic for tc port 11. 2 0 enfrac[10] when set, this bit enables fractional t1/e1 logic for tc port 10. 1 0 enfrac[9] when set, this bit enables fractional t1/e1 logic for tc port 9. 0 0 enfrac[8] when set, this bit enables fractional t1/e1 logic for tc port 8. bit default name description 7 0 ihtxdatshft3 when set to 1, the tx data on the interl eaved highway data bus 3 will be output 1/2 ihtxclk3 cycle later than when the tx inputs are sam pled. set to 0 to disable 1/2 cycle shift. 6 0 ihtxclkpol3 interleaved highw ay bus 3 tx clock polarity. set to 0 for rising edge of ihtxclk3, set to 1 for falling edge. 5 0 ihrxclkpol3 interleaved highway bus 3 rx clock polarity. set to 0 for rising edge of ihtxclk3, set to 1 for falling edge. 4 0 enih3 when set, this bit enables interleaved highway interface for tc ports 12-15. 3 0 enfrac[15] when set, this bit enables fractional t1/e1 logic for tc port 15. 2 0 enfrac[14] when set, this bit enables fractional t1/e1 logic for tc port 14. 1 0 enfrac[13] when set, this bit enables fractional t1/e1 logic for tc port 13. 0 0 enfrac[12] when set, this bit enables fractional t1/e1 logic for tc port 12.
registers 28529-dsh-001-k mindspeed technologies ? 187 mindspeed proprietary and confidential 2.3.19 0xf14?tcctrl4 (tc control register for tc ports 16-19) 2.3.20 0xf15?tcctrl5 (tc control register for tc ports 20-23) bit default name description 7 0 ihtxdatshft4 when set to 1, the tx data on the interl eaved highway data bus 4 will be output 1/2 ihtxclk4 cycle later than when the tx inputs are sam pled. set to 0 to disable 1/2 cycle shift. 6 0 ihtxclkpol4 interleaved highw ay bus 4 tx clock polarity. set to 0 for rising edge of ihtxclk4, set to 1 for falling edge. 5 0 ihrxclkpol4 interleaved highway bus 4 rx clock polarity. set to 0 for rising edge of ihrxclk4, set to 1 for falling edge. 4 0 enih4 when set, this bit enables interleaved highway interface for tc ports 16-19. 3 0 enfrac[19] when set, this bit enables fractional t1/e1 logic for tc port 19. 2 0 enfrac[18] when set, this bit enables fractional t1/e1 logic for tc port 18. 1 0 enfrac[17] when set, this bit enables fractional t1/e1 logic for tc port 17. 0 0 enfrac[16] when set, this bit enables fractional t1/e1 logic for tc port 16. bit default name description 7 0 ihtxdatshft5 when set to 1, the tx data on the interl eaved highway data bus 5 will be output 1/2 ihtxclk5 cycle later than when the tx inputs are sam pled. set to 0 to disable 1/2 cycle shift. 6 0 ihtxclkpol5 interleaved highw ay bus 5 tx clock polarity. set to 0 for rising edge of ihtxclk5, set to 1 for falling edge. 5 0 ihrxclkpol5 interleaved highway bus 5 rx clock polarity. set to 0 for rising edge of ihrxclk5, set to 1 for falling edge. 4 0 enih5 when set, this bit enables interleaved highway interface for tc ports 20-23. 3 0 enfrac[23] when set, this bit enables fractional t1/e1 logic for tc port 23. 2 0 enfrac[22] when set, this bit enables fractional t1/e1 logic for tc port 22. 1 0 enfrac[21] when set, this bit enables fractional t1/e1 logic for tc port 21. 0 0 enfrac[20] when set, this bit enables fractional t1/e1 logic for tc port 20.
registers 28529-dsh-001-k mindspeed technologies ? 188 mindspeed proprietary and confidential 2.3.21 0xf16?tcctrl6 (tc control register for tc ports 24-27) 2.3.22 0xf17?tcctrl7 (tc control register for tc ports 28-31) 2.3.23 0xf18?onesecint (one sec ond interrupt status register) bit default name description 7 0 ihtxdatshft6 when set to 1, the tx data on the interl eaved highway data bus 6 will be output 1/2 ihtxclk6 cycle later than when the tx inputs are sam pled. set to 0 to disable 1/2 cycle shift. 6 0 ihtxclkpol6 interleaved highw ay bus 6 tx clock polarity. set to 0 for rising edge of ihtxclk6, set to 1 for falling edge. 5 0 ihrxclkpol6 interleaved highway bus 6 rx clock polarity. set to 0 for rising edge of ihrxclk6, set to 1 for falling edge. 4 0 enih6 when set, this bit enables interleaved highway interface for tc ports 24-27. 3 0 enfrac[27] when set, this bit enables fractional t1/e1 logic for tc port 27. 2 0 enfrac[26] when set, this bit enables fractional t1/e1 logic for tc port 26. 1 0 enfrac[25] when set, this bit enables fractional t1/e1 logic for tc port 25. 0 0 enfrac[24] when set, this bit enables fractional t1/e1 logic for tc port 24. bit default name description 7 0 ihtxdatshft7 when set to 1, the tx data on the interl eaved highway data bus 7 will be output 1/2 ihtxclk7 cycle later than when the tx inputs are sam pled. set to 0 to disable 1/2 cycle shift. 6 0 ihtxclkpol7 interleaved highw ay bus 7 tx clock polarity. set to 0 for rising edge of ihtxclk7, set to 1 for falling edge. 5 0 ihrxclkpol7 interleaved highway bus 7 rx clock polarity. set to 0 for rising edge of ihrxclk7, set to 1 for falling edge. 4 0 enih7 when set, this bit enables interleaved highway interface for tc ports 28-31. 3 0 enfrac[31] when set, this bit enables fractional t1/e1 logic for tc port 31. 2 0 enfrac[30] when set, this bit enables fractional t1/e1 logic for tc port 30. 1 0 enfrac[29] when set, this bit enables fractional t1/e1 logic for tc port 29. 0 0 enfrac[28] when set, this bit enables fractional t1/e1 logic for tc port 28. bit default name description 7-1 0000000 - reserved, set to zero 0 0 onesecint this bit is the indicator of the one second interrupt
registers 28529-dsh-001-k mindspeed technologies ? 189 mindspeed proprietary and confidential 2.3.24 0xf19?onesecint (one sec ond interrupt control register) 2.4 ima subsystem registers the ima subsystem layer contains configuration and status information that is common to all ima groups. 2.4.1 0x800?ima_ver_1_config (i ma type and version code i) the ima_version i and ii registers contain the type and revision level of the ima core. read-only . 2.4.2 0x801?ima_ver_2_config (ima version codes ii and iii) this register is read-only . bit default name description 7-1 0000000 - reserved, set to zero 0 1 enonesecint when set, this bit enables oneseci nt to appear on the microint* output pin. bit default name description 7?4 ima core type i 0xa = m28529, 32 ports 32 ima groups 0xb = m28525, 16 ports 16 ima groups 3 1 ima core type ii 1 = internal memory present 2?0 version code i 0x4 = m2852x family major revision level bit default name description 7?4 version code ii 4 bit code: 0x4 = m2852x-12 3?0 version code iii 4 bit code: 0x0 = m2852x-12
registers 28529-dsh-001-k mindspeed technologies ? 190 mindspeed proprietary and confidential 2.4.3 0x802?ima_subsys_config (ima configuration control) this register contains some of the basic ima subsystem configuration. 2.4.4 0x803?ima_misc_status (ima miscellaneous status) this register contains miscellaneous status information for the ima subsystem. read-only . bit default name description 7?6 0 link type sets default link type for all ima groups. not used with variable rate facilities 0 = t1 1 = e1 2 = alternate t1 (1.5 44 mbps payload) 3 = alternate e1 (1.9 84 mbps payload) 5?4 0 sram size 0 = 25 ms (e1 mode) 1 = 50 ms 2 = 100 ms 3 = 200 ms 3 0 number of srams 0 = 1 sram, set to 0 for all m2852x devices 2?0 0 number of ports this field indicates the range of valid phy addresses. 0: addresses 0x00?0x03 are valid 1: addresses 0x00?0x07 are valid 2: addresses 0x00?0x0b are valid 3: addresses 0x00?0x0f are valid 4: addresses 0x00?0x13 are valid 5: addresses 0x00?0x17 are valid 6: addresses 0x00?0x1b are valid 7: addresses 0x00?0x1f are valid this field has different ranges depending on product type: m28525: range: 0?3 m28529: range: 0?7 bit default name description 7 ? ? reserved 6 ? ? reserved 5 ? ? reserved 4 ? atm data width this bit indicates whether the atm utopia bus is operating in 16 bit (high) or 8 bit (low) data mode. 3 ? ima_refclk error this bit is set high if a transition detect or for ima_refclk detects a bad signal. this bit is active high and is reset upon reading this address. 2 ? tx atm parity error this bit indicates that a parity erro r has been detected on the transmit atm side utopia bus. this bit is active high and is reset upon reading this address. 1 ? ? reserved. 0 ? rx phy parity error this bit indicates that a parity error has been detected on the receive phy side cell bus. this bit is active high and is reset upon reading this address.
registers 28529-dsh-001-k mindspeed technologies ? 191 mindspeed proprietary and confidential 2.4.5 0x804?ima_misc_config (ima miscellaneous control) this register contains some of the basic ima subsystem configuration. 2.4.6 0x805?ima_mem_low_test (ima memory test addr ess (bits 0?7)) registers 0x805?0x808 are used to perform memory diagnostic tests on the internal or external differential delay sram. bit default name description 7 ? ? reserved. set to 0 6 0 alternate gtsm mode 1 = when the gtsm is down, atmutxcl av for that group is contro lled as if all configured links in the group are active. 0 = when the gtsm is down, atmutxclav for that group is inactive. 5?4 0 phy size this two bit field determines the use of the phy side clav and enb* signals. when using utopia-to-serial mode, phy size should be set to 16 ports per clav and en*. thus for m28525, phy size should be 2 while for m28529, phy size should be 1. 0 = clav and en* for every 4 phy addresses (support 8 ports total) (ports 0-3 assigned to clav0/enb0*) (ports 4-7 assigned to clav1/en1*) 1 = clav and en* for every 16 phy addresses (support 32 ports total) (ports 0-15 assigned to clav0/enb0*) (ports 16-31 assigned to clav1/enb1*) 2 = clav and en* for all phy a ddresses (support 32 ports total) (ports 0-31 assigned to clav0/enb0*) for utopia-to-utopia mode, ph yurxena[1] and phyutxena[1] should be pull high when phy size is set to 2. 3 = clav and en* for every 8 phy addresses (support 16 ports total) (ports 0-7 assigned to clav0/enb0*) (ports 8-15 assigned to clav1/enb1*) 3 0 enable external hec checker 1 = bit 7 of the hec byte is a hec error flag 0 = use the hec error checker within the ima block 2 0 check atmutxaddr[4] and atmurxaddr[4] 0 = mask bits (don?t care) 1 = check atmutxaddr[4] and tmurxaddr[4] for correct value 1 0 check atmutxaddr[3] and atmurxaddr[3] 0 = mask bits (don?t care) 1 = check atmutxaddr[3] and atmurxaddr[3] for correct value 0 0 check atmutxaddr[2] and atmurxaddr[2] 0 = mask bits (don?t care) 1 = check atmutxaddr[2] and atmurxaddr[2] for correct value bit default name description 7?0 0x00 memory test address this field contai ns the least significant bits of the me mory test address for the selected memory component. range: 0x00?0xff
registers 28529-dsh-001-k mindspeed technologies ? 192 mindspeed proprietary and confidential 2.4.7 0x806?ima_mem_hi_test (ima memory test addr ess (bits 8?15)) 2.4.8 0x807?ima_mem_test_ctl (ima me mory test control / address msbs) 2.4.9 0x808?ima_mem_test_data (ima memory test data) 2.4.10 0x809?ima_lnk_diag_ctl (ima link diagnostic control register) this register is used to specify a port number for observ ation of link differential delay and anomalies. the contents of this register are used to report the link informatio n via registers 0x809?0x80b. bit 5 of this register is read-only . 2.4.11 0x80a?ima_lnk_diff_del (ima li nk differential de lay write counter) this register, along with bit 5 of address 0x809, reports the value of the sram write phase at the time when the read phase is 0. this phase information is used to calculate the link differential delay. bit default name description 7?0 0x00 memory test address this field contains the mi ddle significant bits of the memo ry test address for the selected memory component. range: 0x00?0xff bit default name description 7 0 memory test address bit 20 this field contains the mo st significant bit of the memory t est address for the selected memory component. 6?4 0 ram test access 0 = no test selected, normal operation 1 = sram test 2?7 = reserved 3?0 0 memory test address bits 19?16 this field contains the most sign ificant bits of the memory test address for the selected memory component. range: 0x00?0x0f bit default name description 7?0 0x00 memory test data this fiel d contains the data to be written or read from the memory test address for the selected memory component. range: 0x00?0xff bit default name description 7 ? ? reserved. set to 0 6 ? ? reserved. set to 0 5 ? link delay write counter this field contains the most significant bit of the sram write counter for the diagnostic link (selected using the field below). 4?0 0x00 link diagnostic phy address this field contains the phy cell bus address of the port for which a diagnostic measurement is to be performed. range: 0x00?0x1f
registers 28529-dsh-001-k mindspeed technologies ? 193 mindspeed proprietary and confidential 2.4.12 0x80b?ima_rcv_lnk_anomalie s (ima receive link anomalies) these anomalies are for the diagnostic link selected using address 0x809. the bits in this register are read-only and are cleared upon read. bit default name description 7?0 ? link delay write counter this field contains a snapshot of 8 of the least significan t bits of the sram write counter for the diagnostic link (selected using address 0x809). all others (range: 0x00?0xff) delay window = 0 (see register 0x815): value = cell_count >> 1 delay window = 1?3 (see regist er 0x815): value = cell_count delay window = 4 (see register 0x815): value = cell_count >> 2 bit default name description 7 ? icp-err anomaly 1 = icp-err anomal y was active sometime since the l ast time this register was read 0 = icp-err defect was inactive 6 ? icp-inv anomaly? unexpected ima label 1 = unexpected ima label condition of the icp-in v anomaly was active some time since the last time this register was read 0 = unexpected ima label condition was inactive 5 ? icp-inv anomaly? unexpected lid 1 = unexpected lid condition of the icp-inv anom aly was active sometime since the last time this register was read 0 = unexpected lid condition was inactive 4 ? icp-inv anomaly? unexpected ima id 1 = unexpected ima id condition of the icp-inv anomaly was active some time since the last time this register was read 0 = unexpected ima id condition was inactive 3 ? icp-inv anomaly? unexpected m 1 = unexpected m condition of the icp-inv anomal y was active sometime since the last time this register was read 0 = unexpected m condition was inactive 2 ? icp-inv anomaly? unexpected ima frame number 1 = unexpected ima frame number condition of the icp-inv anomaly was active sometime since the last time th is register was read 0 = unexpected ima frame numb er condition was inactive 1 ? icp-inv anomaly? unexpected ima cell offset 1 = unexpected ima cell offset condition of the icp-inv anomal y was active sometime since the last time this register was read 0 = unexpected ima cell offset condition was inactive 0 ? icp-mis anomaly 1 = icp-mis anomal y was active sometime since the last time this register was read 0 = icp-mis defect was inactive
registers 28529-dsh-001-k mindspeed technologies ? 194 mindspeed proprietary and confidential 2.4.13 0x80c?ima _phy_loopback (i ma phy side utopia loopback) this register controls the utopia loopbacks on the phy side of the ima block. 2.4.14 0x80e?ima_diag_xor_bit (ima diagnostic bit) this register provides a single bit that can be used by a diagnostic test routine to verify the connectivity of the microprocessor address lines to the ima device. this bit is read-only . 2.4.15 0x80f?ima_diag (ima diagnostic register) this register provides an isolated 8 bit storage register that can be used by a diagnostic test routine to verify the connectivity of the microprocessor data lines to the ima device. bit default name description 7-3 ? ? reserved. set to 0 2 ? loopback enable 0 = phy side loopback disabled. 1 = phy side loopback enabled per bits 1:0 of this register. 1-0 ? loopback type(s) 0 = ima system loopback 0 -- us es txclav signal(s) from phy (tc or external) 1 = ima system loopback 1 -- ignores txclav signal(s) from phy layer 2 = ima line loopback -- ignores txclav signal(s) from phy layer 3 = not defined bit default name description 7 ? ? reserved. 6 ? ? reserved. 5 ? ? reserved. 4 ? ? reserved. 3 ? ? reserved. 2 ? ? reserved. 1 ? ? reserved. 0 ? address diagnostic bit exclusive or of address bits from previous ima core read access. the number of bits in the exclusive or operation is 11. bit default name description 7?0 0x00 data diagnostic register an 8 bit register that can be written and read by the processor. the register is not used within the ima block.
registers 28529-dsh-001-k mindspeed technologies ? 195 mindspeed proprietary and confidential 2.4.16 0x810?ima_tim_ref_mux_ctl_ addr (ima timing reference multiplexer control address) this register is used in conjunction with 0x811 to conf igure various timing elements within the ima core. register 0x810 and 0x811 are an indirect register pair in that a pa rticular timing element is selected using register 0x810 and the configuration for that timing element is programmed using register 0x811. bit default name description 7?6 0 multiplexer type 0 = set timing reference for a rx ima group 1 = set timing reference for a tx ima group 2 = set timing source for tx_trl outputs 3 = set the clock divisor for an ima group 5 ? ? reserved. set to 0. 4?0 0 multiplexer id for multiplexer type = 0, mult iplexer type = 1, and multiplexer type = 3: m28525: 0?0xf: ima group 1?16 m28529: 0?0x1f: ima group 1?32 for multiplexer type = 2: 0?1: tx_trl[0]?tx_trl[1] output
registers 28529-dsh-001-k mindspeed technologies ? 196 mindspeed proprietary and confidential 2.4.17 0x811?ima_tim_ref_mux_ctl_ data (ima timing reference multiplexer control data) bit default name description 7 ? ? reserved. set to 0. 6 ? ? reserved. set to 0. for multiplexer type 0 and 1 5?0 0x00 timing source 0x00?0x1f: select timing from a receive port (see register 0x816) m28525: 0?0xf: port 0?15 m28529: 0?0x1f: port 0?31 0x20: use ima_sysclk/24 or dsl genera tor output as source (see register 0x816) 0x21: use ima_refclk as source for multiplexer type 2 5?0 0x00 timing source 0x00?0x1f: select timing from a receive port (see register 0x816) m28525: 0?0xf: port 0?15 m28529: 0?0x1f: port 0?31 0x20: ima_sysclk/24 0x21: ima_refclk 0x22: 8 khz for multiplexer type 3 5 ? ? reserved. set to 0. 4 ? ? reserved. set to 0. 3?0 0x0 clock divisor this field contains the clock divider multiplier for the group. the ima group number is set by writing to the multiplexer id field in address 0x810. 0 = based on link type field in address 0x002 1 = 1/1 2 = 192/193 3 = 15/16
registers 28529-dsh-001-k mindspeed technologies ? 197 mindspeed proprietary and confidential 2.4.18 0x812?ima_rx_persist_con fig (ima receive persistence configuration) 2.4.19 0x813?ima_atm_utopia_bus_ctl (ima atm utopia bus control) this register configures the operation of the atm side utopia bus and the sample time of phyutxclav for an ima group. bit default name description 7 0 ? reserved. set to 0. 6 0 alpha value (1) 0: = 1 1: = 2 5?3 0 beta value (2) 0: = 1 1: = 2 2: = 3 3: = 4 4: = 5 2?0 0 gamma value (3) 0: = 1 1: = 2 2: = 3 3: = 4 4: = 5 footnote: (1) the alpha value is the number of c onsecutive invalid icp cells needed for the link to leave the ima sync state. (2) the beta value is the number of c onsecutive errored icp cells needed for the link to leave the ima sync state. (3) the gamma value is the number of c onsecutive valid icp cells needed for the link to enter the ima sync state. bit default name description 7 ? ? reserved. set to 0. 6 0 atm address mode 0 = utopia level 2 (multiple addresses) 1 = utopia level 1 (single fixed address, no address latching) 5 0 ? reserved. set to 0. 4 0 atmurxclav mode 0 = atmurxclav is set act ive for selected channel during cell transfer 1 = atmurxclav is set inactive for selected channel during cell transfer 3 0 atmutxclav last 4 bytes/words mode 0 = atmutxclav is forced inactive/active (based on the state of bit 2) du ring last 4 bytes/words for selected channel during cell transfer 1 = atmutxclav reflects true ce ll available status during last 4 bytes/words for selected channel during cell transfer 2 0 atmutxclav mode 0 = atmutxclav is set inact ive for selected channe l during cell transfer 1 = atmutxclav is set active for selected channel during cell transfer 1 0 clav three-state disable 0 = atmurxclav a nd atmutxclav threestate when not selected 1 = atmurxclav and atmutxclav do not threestate 0 0 phyutxclav sample time 0 = for an ima group, sample phyutxclav during an icp cell to determine sicp rate 1 = for an ima group, delay sampling phyutxclav until >5 payload byte periods after an icp transfer
registers 28529-dsh-001-k mindspeed technologies ? 198 mindspeed proprietary and confidential 2.4.20 0x814?ima_diff_del ay_addr (ima differentia l delay control address) this register is used in conjunction with 0x815 to configur e the differential delay operation of the ima core. register 0x814 and 0x815 are an indirect register pair in that a pa rticular ima group is selected using register 0x814 and the configuration for that ima group is programmed using register 0x815. 2.4.21 0x815?ima_diff_delay_data (ima differential delay control data) bit default name description 7 ? ? reserved. set to 0. 6 0 control type 0 = set delay threshold for an ima group 1 = set delay window for an ima group 5 ? ? reserved. set to 0. 4?0 0x0 group number m28525: 0?0xf: ima group 1?16 m28529: 0?0x1f: ima group 1?32 bit default name description for control type = 0 7?0 0x00 differential delay threshold this field contains the cell offset that corresponds to differenti al delay threshold setting for the group. delay window = 0, 5: value = 255?(cell_count >> 1) delay window = 1?3, 6?7: value = 255?cell_count delay window = 4: value = 255?(cell_count >> 2) for control type = 1 7 ? ? reserved. set to 0. 6 ? ? reserved. set to 0. 5 ? ? reserved. set to 0. 4 ? ? reserved. set to 0. 3 ? ? reserved. set to 0. 2?0 delay window this field contains the number of im a frames (assuming m=128) that are examined when setting the differential delay buf fer. this field is set based on the facility payload rate. 0 = 8 frames (1024 cells), for payload rates 1024 kbps 1 = 4 frames (512 cells), fo r 1024 kbps > payload rates 512 kbps 2 = 2 frames (256 cells), fo r 512 kbps > payload rates 256 kbps 3 = 1 frame (128 cells), fo r payload rates < 256 kbps 4 = 16 frames (2048 ce lls), for payload rates 1024 kbps 5 = 8 frames (1024 cells), fo r 1024 kbps > payload rates 512 kbps 6 = 4 frames (512 cells), fo r 512 kbps > payload rates 256 kbps 7 = 2 frame (256 cells), fo r payload rates < 256 kbps
registers 28529-dsh-001-k mindspeed technologies ? 199 mindspeed proprietary and confidential 2.4.22 0x816?ima_dsl_clock_gen_addr (ima dsl clock generator control) this register is used in conjunction with 0x817 to configure the operation of the dsl clock generator in the ima core. register 0x816 and 0x817 are an indirect register pair in that a particular clock generator element is selected using register 0x816 and the configuration for t hat element is programmed using register 0x817. the overall operation of the clock generators are governed by the following equations: prescaler factor = prescaler numera tor / (prescaler terminal count + 1) intermediate frequency = reference clock frequency * prescaler factor reference denominator = 257 + reference clock divisor 8 khz = intermediate frequency / (reference denominator) link payload rate = 8 kbps * (mul tiplier factor) * (rate multiplier) a further constraint is: (maximum link payload rate) / (rate multiplier) intermediate frequency ima_sysclk/16 in a typical g.shdsl application, intermediate frequency is set to 2.56 mhz, rate multiplier = 1, and the reference denominator is set to 320. other settings are possible as long as the above equations and constraints are met. bit default name description 7?5 0 control type 0 = basic setup 1 = pre-scaler and reference divisor setup 2 = tx ima group factor lsbs 3 = tx ima group factor msb 4 = rx ima group factor lsbs 5 = rx ima group factor msb 6 = rx timing synthesizer factor lsbs 7 = rx timing synthesizer factor msb for control type = 0 4?0 ? ? reserved. set to 0. for control type = 1 4-2 ? ? reserved. set to 0. 1-0 ? sub type 0 = pre-scaler terminal count 1 = pre-scalar numerator 2 = reference divisor 3 = reserved for control type = 2, 3, 4, 5 4?0 0x0 group number m28525: 0?0xf: ima group 1?16 m28529: 0?0x1f: ima group 1?32 for control type = 6, 7 4?0 0x00 port number m28525: 0?0xf: port 0?15 m28529: 0?0x1f: port 0?31
registers 28529-dsh-001-k mindspeed technologies ? 200 mindspeed proprietary and confidential 2.4.23 0x817?ima_dsl_clock_gen_data (ima_dsl clock generator data) this register is used in conjunction with 0x816 to configure the operation of the dsl clock generator in the ima core. register 0x816 and 0x817 are an indirect register pair in that a particular clock generator element is selected using register 0x816 and the configuration for t hat element is programmed using register 0x817. bit default name description for control type = 0 7 ? ? reserved. set to 0. 6 0 enrxsyn enable rx timing synthesizers 0 = use sprxclk inputs 1 = use synthesizers in stead of sprxclk inputs 5 0 dslclkgen substitute dsl clock generator 0 = use ima_sysclk/ 24 in ima group clock and tx_trl selectors 1 = use dsl clock generator outputs when ti ming source is set to 0x20 in register 0x811. 4 0 ima_clksel 0 = use ima_sysclk as input to dsl clock generators 1 = use ima_refclk as input to dsl clock generators 3?0 ? ? reserved. set to 0. for control type = 1/sub-type = 0 7?0 0x00 pre-scaler terminal count this field contains the terminal count of the pr e-scaler clock divider. the pre-scaler denominator is the value of this field plus 1. for control type = 1/sub-type = 1 7?0 0x00 pre-scaler numerator this field cont ains the numerator for the pre-scaler. for control type = 1/sub-type = 2 7-0 0x00 reference clock divisor this field contains 8 of the 9 bits of the terminal count for the reference clock divisor. the reference clock divisor counts from 0 to the termin al count which is given by the value of this field plus 257. as an example if the value of this register is 63 decimal, then the reference clock divisor will be 320. for control type = 2, 4 7?0 0x00 group clock multiplier factor (lsbs) this register contains the 8 lsbs of the payload bandwidth for the ports used in the ima group. the contents of this register ar e multiplied by 8kbps and the rate multiplier in order to obtain the bandwidth. for control type = 3, 5 7-6 ? ? reserved. set to 0. 5-4 0 rate multiplier scale factor used to ge nerate link rates > intermediate frequency 0 = multiply rate by 1 (typically used by link rates < 3.072 mbps) 1 = multiply rate by 2 (t ypically used by 3.072 < link rates < 6.144 mbps) 2 = multiply rate by 4 (typically used by link rates > 6.144 mbps) 3 = not defined. 3-1 ? ? reserved. set to 0. 0 0 group clock multiplier factor (msb) this register contains the msb of the payload bandwidth for the ports used in the ima group. the contents of this register are multiplied by 2048kbps and the rate multiplier in order to obtain the bandwidth.
registers 28529-dsh-001-k mindspeed technologies ? 201 mindspeed proprietary and confidential 2.4.24 0x818?ima_rx_trans_table (ima receive transla tion table address) this register is used in conjunction with 0x819 fo r configure the translation between the atm side utopia addresses and the internal channels (bypass ports and ima groups) associated with the ima core. register 0x818 and 0x819 are an indirect register pair in that a address is selected using register 0x818 and the configuration for that address is programmed using register 0x819. for control type = 6 7?0 0x00 port clock multiplier factor (lsbs) this register contains the 8 lsbs of the payloa d bandwidth for the specific port of the rx timing clock synthesizer. the contents of this register ar e multiplied by 8kbps and the rate multiplier in order to obtain the bandwidth. for control type = 7 7?6 ? ? reserved. set to 0. 5-4 0 rate multiplier scale factor used to ge nerate link rates > intermediate frequency 0 = multiply rate by 1 (typically used by link rates < 3.072 mbps) 1 = multiply rate by 2 (t ypically used by 3.072 < link rates < 6.144 mbps) 2 = multiply rate by 4 (typically used by link rates > 6.144 mbps) 3 = not defined. 3?1 ? ? reserved. set to 0. 0 0 port clock multiplier factor (msb) this register contains the msb of the payload ba ndwidth for the specific port of the rx timing clock synthesizer. the contents of this register are multiplied by 2048kbps and the rate multiplier in order to obtain the bandwidth. bit default name description 7 0 translation type 0 = the value in bits 5?0 enable s atm address ?> ima internal channel translations 1 = the value in bits 5?0 enables ima in ternal channel ?> atm address translations 6 ? ? don?t care. ignore. for translation type = 0 5 ? ? don?t care. ignore. 4?0 0x00 atm utopia address for type 0, this field contains the atm side utopia address. range: 0x00?0x1f for translation type = 1 5?0 0x00 internal ima channel for type 1, this field contains the ima internal channel address. range 0x00?0x1f: receive port m28525: 0?0xf: port 0?15 m28529: 0?0x1f: port 0?31 range 0x20?0x3f: ima group m28525: 0x20?0x2f: ima group 1?16 m28529: 0x20?0x3f: ima group 1?32 bit default name description (continued)
registers 28529-dsh-001-k mindspeed technologies ? 202 mindspeed proprietary and confidential 2.4.25 0x819?ima_rx_atm_trans_tabl e (ima receive atm translation table internal channel) this register is used in conjunction with 0x818 fo r configure the translation between the atm side utopia addresses and the internal channels (bypass ports and ima groups) associated with the ima core. register 0x818 and 0x819 are an indirect register pair in that an address is selected using register 0x818 and the configuration for that address is programmed using register 0x819. bit default name description for translation type = 0 7 ? ? don?t care. ignore. 6 1 internal ima channel 1=atm address is not assigned to this device 0=atm address is assi gned to this device 5-0 ? ? don?t care. ignore. for translation type = 1 7 0 channel active 1 = internal channel active 0 = internal channel inactive 6 ? ? don?t care. ignore. 5 ? ? don?t care. ignore. 4?0 0x00 atm utopia address this field contains the mapping for the internal ima channel set in register 0x818. range: 0x00?0x1f
registers 28529-dsh-001-k mindspeed technologies ? 203 mindspeed proprietary and confidential 2.4.26 0x81b?ima_tx_trans_t able (ima transmit translation table address) this register is used in conjunction with 0x81c for configure the translation between the atm side utopia addresses and the internal channels (bypass ports and ima groups) associated with the ima core. register 0x81b and 0x81c are an indirect register pair in that a address is selected using register 0x81b and the configuration for that address is programmed using register 0x81c. 2.4.27 0x81c?ima_tx_atm_trans_table (transmit atm translation table internal channel) this register is used in conjunction with 0x81b for configure the translation between the atm side utopia addresses and the internal channels (bypass ports and ima groups) associated with the ima core. register 0x81b and 0x81c are an indirect register pair in that a address is selected using register 0x81b and the configuration for that address is programmed using register 0x81c. bit default name description 7 0 translation type 0 = the value in bits 5?0 enable s atm address ?> ima internal channel translations 1 = the value in bits 5?0 enables ima in ternal channel ?> atm address translations 6 ? ? don?t care. ignore. for translation type = 0 5 ? ? don?t care. ignore. 4?0 0x00 atm utopia address for type 0, this field contains the atm side utopia address. range: 0x00?0x1f for translation type = 1 5?0 0x00 internal ima channel for type 1, this field contains the ima internal channel address. range 0x00?0x1f: transmit port m28525: 0?0xf: port 0?15 m28529: 0?0x1f: port 0?31 range 0x20?0x3f: ima group m28525: 0x20?0x2f: ima group 1?16 m28529: 0x20?0x3f: ima group 1?32 bit default name description for translation type = 0 7 ? ? don?t care. ignore. 6 1 internal ima channel 1=atm address is not assigned to this device 0=atm address is assigned to this device 5-0 ? ? don?t care. ignore
registers 28529-dsh-001-k mindspeed technologies ? 204 mindspeed proprietary and confidential 2.5 ima group the ima group layer contains configuration and status information that is associated with ima groups. 2.5.1 0x81f?ima_grp_1to4_se m (group table control i) for the following bits, 1 = the group table is being updated, 0 = the group table is not being updated. the update enable must be set to 1 prior to writing the group table. all elements of the group table must be re-written. after writing to all 8 elements, the update enable is reset to 0. the group tables are described below. 2.5.2 0x91f?ima_grp_5to8_se m (group table control ii) for the following bits, 1 = the group table is being updated, 0 = the group table is not being updated. the update enable must be set to 1 prior to writing the group table. all elements of the group table must be re-written. after writing to all 8 elements, the update enable is reset to 0. the group tables are described below. for translation type = 1 7 0 channel active 1 = internal channel active 0 = internal channel inactive 6 ? ? don?t care. ignore. 5 ? ? don?t care. ignore. 4?0 0x00 atm utopia address this field contains the mapping for the internal ima channel set in register 0x81b. range: 0x00?0x1f note: this register cannot be read back. bit default name description 7 0 update enable for receive group 4 addresses 0x8dc?0x8df 6 0 update enable for receive group 3 addresses 0x8d8?0x8db 5 0 update enable for receive group 2 addresses 0x8d4?0x8d7 4 0 update enable for receive group 1 addresses 0x8d0?0x8d3 3 0 update enable for transmit group 4 addresses 0x838?0x83f 2 0 update enable for transmit group 3 addresses 0x830?0x837 1 0 update enable for transmit group 2 addresses 0x828?0x82f 0 0 update enable for transmit group 1 addresses 0x820?0x827 note: this register cannot be read back. bit default name description
registers 28529-dsh-001-k mindspeed technologies ? 205 mindspeed proprietary and confidential 2.5.3 0xa1f?ima_grp_9to12_sem (group table control iii) for the following bits, 1 = the group table is being updated, 0 = the group table is not being updated. the update enable must be set to 1 prior to writing the group table. all elements of the group table must be re-written. after writing to all 8 elements, the update enable is reset to 0. the group tables are described below. bit default name description 7 0 update enable for receive group 8 addresses 0x9dc?0x9df 6 0 update enable for receive group 7 addresses 0x9d8?0x9db 5 0 update enable for receive group 6 addresses 0x9d4?0x9d7 4 0 update enable for receive group 5 addresses 0x9d0?0x9d3 3 0 update enable for transmit group 8 addresses 0x938?0x93f 2 0 update enable for transmit group 7 addresses 0x930?0x937 1 0 update enable for transmit group 6 addresses 0x928?0x92f 0 0 update enable for transmit group 5 addresses 0x920?0x927 note: this register cannot be read back. bit default name description 7 0 update enable for receive group 12 addresses 0xadc?0xadf 6 0 update enable for receive group 11 addresses 0xad8?0xadb 5 0 update enable for receive group 10 addresses 0xad4?0xad7 4 0 update enable for receive group 9 addresses 0xad0?0xad3 3 0 update enable for transmit group 12 addresses 0xa38?0xa3f 2 0 update enable for transmit group 11 addresses 0xa30?0xa37 1 0 update enable for transmit group 10 addresses 0xa28?0xa2f 0 0 update enable for transmit group 9 addresses 0xa20?0xa27
registers 28529-dsh-001-k mindspeed technologies ? 206 mindspeed proprietary and confidential 2.5.4 0xb1f?ima_grp_13to16_sem (group table control iv) for the following bits, 1 = the group table is being updated, 0 = the group table is not being updated. the update enable must be set to 1 prior to writing the group table. all elements of the group table must be re-written. after writing to all 8 elements, the update enable is reset to 0. the group tables are described below. 2.5.5 0xc1f?ima_grp_17to20_sem (gro up table control v (m28529 only)) for the following bits, 1 = the group table is being updated, 0 = the group table is not being updated. the update enable must be set to 1 prior to writing the group table. all elements of the group table must be re-written. after writing to all 8 elements, the update enable is reset to 0. the group tables are described below. note: this register cannot be read back. bit default name description 7 0 update enable for receive group 16 addresses 0xbdc?0xbdf 6 0 update enable for receive group 15 addresses 0xbd8?0xbdb 5 0 update enable for receive group 14 addresses 0xbd4?0xbd7 4 0 update enable for receive group 13 addresses 0xbd0?0xbd3 3 0 update enable for transmit group 16 addresses 0xb38?0xb3f 2 0 update enable for transmit group 15 addresses 0xb30?0xb37 1 0 update enable for transmit group 14 addresses 0xb28?0xb2f 0 0 update enable for transmit group 13 addresses 0xb20?0xb27 note: this register cannot be read back. bit default name description 7 0 update enable for receive group 20 addr esses 0xc5c?0xc5f (not defined for m28525) 6 0 update enable for receive group 19 addresses 0xc58?0xc5b (not defined for m28525) 5 0 update enable for receive group 18 addr esses 0xc54?0xc57 (not defined for m28525) 4 0 update enable for receive group 17 addr esses 0xc50?0xc53 (not defined for m28525) 3 0 update enable for transmit group 20 addresses 0xc38?0xc3f (not defined for m28525) 2 0 update enable for transmit group 19 a ddresses 0xc30?0xc37 (not defined for m28525) 1 0 update enable for transmit group 18 addresses 0xc28?0xc2f (not defined for m28525) 0 0 update enable for transmit group 17 a ddresses 0xc20?0xc27 (not defined for m28525)
registers 28529-dsh-001-k mindspeed technologies ? 207 mindspeed proprietary and confidential 2.5.6 0xc9f?ima_grp_21to24_sem (gro up table control v (m28529 only)) for the following bits, 1 = the group table is being updated, 0 = the group table is not being updated. the update enable must be set to 1 prior to writing the group table. all elements of the group table must be re-written. after writing to all 8 elements, the update enable is reset to 0. the group tables are described below. 2.5.7 0xd1f?ima_grp_25to 28_sem (group table co ntrol v (m28529 only)) for the following bits, 1 = the group table is being updated, 0 = the group table is not being updated. the update enable must be set to 1 prior to writing the group table. all elements of the group table must be re-written. after writing to all 8 elements, the update enable is reset to 0. the group tables are described below. note: this register cannot be read back. bit default name description 7 0 update enable for receive group 24 addresses 0xcdc?0xcdf (not defined for m28525) 6 0 update enable for receive group 23 addresses 0xcd8?0xcdb (not defined for m28525) 5 0 update enable for receive group 22 addresses 0xcd4?0xcd7 (not defined for m28525) 4 0 update enable for receive group 21 addresses 0xcd0?0xcd3 (not defined for m28525) 3 0 update enable for transmit group 24 addresses 0xcb8?0xcbf (not defined for m28525) 2 0 update enable for transmit group 23 addresses 0xcb0?0xcb7 (not defined for m28525) 1 0 update enable for transmit group 22 addresses 0xca8?0xcaf (not defined for m28525) 0 0 update enable for transmit group 21 addresses 0xca0?0xca7 (not defined for m28525) note: this register cannot be read back. bit default name description 7 0 update enable for receive group 28 addresses 0xd5c?0xd5f (not defined for m28525) 6 0 update enable for receive group 27 addresses 0xd58?0xd5b (not defined for m28525) 5 0 update enable for receive group 26 addresses 0xd54?0xd57 (not defined for m28525) 4 0 update enable for receive group 25 addresses 0xd50?0xd53 (not defined for m28525) 3 0 update enable for transmit group 28 addresses 0xd38?0xd3f (not defined for m28525) 2 0 update enable for transmit group 27 addresses 0xd30?0xd37 (not defined for m28525) 1 0 update enable for transmit group 26 addresses 0xd28?0xd2f (not defined for m28525) 0 0 update enable for transmit group 25 addresses 0xd20?0xd27 (not defined for m28525)
registers 28529-dsh-001-k mindspeed technologies ? 208 mindspeed proprietary and confidential 2.5.8 0xd9f?ima_grp_29to 32_sem (group table co ntrol v (m28529 only)) for the following bits, 1 = the group table is being updated, 0 = the group table is not being updated. the update enable must be set to 1 prior to writing the group table. all elements of the group table must be re-written. after writing to all 8 elements, the update enable is reset to 0. the group tables are described below. 2.5.9 ima_tx_grp n _rx_test_pattern (transmit group rx test pattern) this register contains the value of the rx test pattern field for the transmitted icp cells. note: this register cannot be read back. bit default name description 7 0 update enable for receive group 32 addr esses 0xddc?0xddf (not defined for m28525) 6 0 update enable for receive group 31 addr esses 0xdd8?0xddb (not defined for m28525) 5 0 update enable for receive group 30 addr esses 0xdd4?0xdd7 (not defined for m28525) 4 0 update enable for receive group 29 addr esses 0xdd0?0xdd3 (not defined for m28525) 3 0 update enable for transmit group 32 addresses 0xdb8?0xdbf (not defined for m28525) 2 0 update enable for transmit group 31 addresses 0xdb0?0xdb7 (not defined for m28525) 1 0 update enable for transmit group 30 addresses 0xda8?0xdaf (not defined for m28525) 0 0 update enable for transmit group 29 addresses 0xda0?0xda7 (not defined for m28525) group 1?16 address n =1 n =2 n =3 n =4 n =5 n =6 n =7 n =8 n =9 n =10 n =11 n =12 n =13 n =14 n =15 n =16 0x820 0x828 0x830 0x838 0x920 0x928 0x930 0x938 0xa20 0xa28 0xa30 0xa38 0xb20 0xb28 0xb30 0xb38 m28525 m28529 group 17?32 address n =17 n =18 n =19 n =20 n =21 n =22 n =23 n =24 n =25 n =26 n =27 n =28 n =29 n =30 n =31 n =32 0xc20 0xc28 0xc30 0xc38 0xca 0 0xca 8 0xcb 0 0xcb 8 0xd2 0 0xd2 8 0xd3 0 0xd3 8 0xda 0 0xda 8 0xdb 0 0xdb 8 m28525 -- not applicable m28529
registers 28529-dsh-001-k mindspeed technologies ? 209 mindspeed proprietary and confidential 2.5.10 ima_tx_grp n _ctl (transmit group control register) this register, in conjunction with the ima_tx_grp n _first_phy_addr register, controls the operation of the transmit ima group. bit default name description 7?0 0x00 rx test pattern in support of the test pattern procedur e, this field is set equal to the value acquired from the receive side test link. see address 0x8e7. when the test pattern procedure is inactive, the rx test pattern field should be set to 0xff. range: 0x00?0xff group 1?16 address n =1 n =2 n =3 n =4 n =5 n =6 n =7 n =8 n =9 n =10 n =11 n =12 n =13 n =14 n =15 n =16 0x821 0x829 0x831 0x839 0x921 0x929 0x931 0x939 0xa21 0xa29 0xa31 0xa39 0xb21 0xb29 0xb31 0xb39 m28525 m28529 group 17?32 address n =17 n =18 n =19 n =20 n =21 n =22 n =23 n =24 n =25 n =26 n =27 n =28 n =29 n =30 n =31 n =32 0xc21 0xc29 0xc31 0xc39 0xca 1 0xca 9 0xcb 1 0xcb 9 0xd2 1 0xd2 9 0xd3 1 0xd3 9 0xda 1 0xda 9 0xdb 1 0xdb 9 m28525 -- not applicable m28529 bit default name description 7 0 group enable 1 = group is established and a round-robin is created 0 = group is not established 6 0 sw timeout expired 1 = certain lsm transitions (unusable usable, usable active) are allowed 0 = certain lsm transitions (unusable usable, usable active) are blocked 5 ? ? reserved. set to 0. 4?0 0x0 group size sets the number of configured links within group. range: 0x0?0x1f (1?32 links in group)
registers 28529-dsh-001-k mindspeed technologies ? 210 mindspeed proprietary and confidential 2.5.11 ima_tx_grp n _first_phy_addr (transmit first phy address) this register, in conjunction with the ima_tx_grp n _ctl register, controls the operation of the transmit ima group. group 1?16 address n =1 n =2 n =3 n =4 n =5 n =6 n =7 n =8 n =9 n =10 n =11 n =12 n =13 n =14 n =15 n =16 0x82 2 0x82a 0x83 2 0x83a 0x92 2 0x92a 0x93 2 0x93a 0xa2 2 0xa2a 0xa3 2 0xa3a 0xb2 2 0xb2a 0xb3 2 0xb3a m28525 m28529 group 17?32 address n =17 n =18 n =19 n =20 n =21 n =22 n =23 n =24 n =25 n =26 n =27 n =28 n =29 n =30 n =31 n =32 0xc22 0xc2 a 0xc32 0xc3 a 0xca 2 0xca a 0xcb 2 0xcb a 0xd2 2 0xd2 a 0xd3 2 0xd3 a 0xda 2 0xda a 0xdb 2 0xdb a m28525 -- not applicable m28529 bit default name description 7 ? ? reserved. set to 0. 6 0 group inhibit 1 = group is inhibited from carrying traffic 0 = group is not inhibited 5 0x0 tx ima version ima oam label value 1 = ima v1.1 0 = ima v1.0 4?0 0x00 link phy address this field contains the phy port addre ss of the transmit link with the lowest lid in the group. m28525: range: 0?0xf m28529: range: 0?0x1f
registers 28529-dsh-001-k mindspeed technologies ? 211 mindspeed proprietary and confidential 2.5.12 ima_tx_grp n _id (transmit group id) this register contains the value of the ima group id field for the transmitted icp cells. group 1?16 address n =1 n =2 n =3 n =4 n =5 n =6 n =7 n =8 n =9 n =10 n =11 n =12 n =13 n =14 n =15 n =16 0x82 3 0x82b 0x83 3 0x83b 0x923 0x92b 0x933 0x93b 0xa2 3 0xa2b 0xa3 3 0xa3b 0xb2 3 0xb2b 0xb3 3 0xb3b m28525 m28529 group 17?32 address n =17 n =18 n =19 n =20 n =21 n =22 n =23 n =24 n =25 n =26 n =27 n =28 n =29 n =30 n =31 n =32 0xc23 0xc2 b 0xc33 0xc3 b 0xca 3 0xca b 0xcb 3 0xcb b 0xd2 3 0xd2 b 0xd3 3 0xd3 b 0xda 3 0xda b 0xdb 3 0xdb b m28525 -- not applicable m28529 bit default name description 7?0 0x00 tx group id this field contains the transmit group id sent in the transmit icp cells of all links within the group. range: 0x00?0xff
registers 28529-dsh-001-k mindspeed technologies ? 212 mindspeed proprietary and confidential 2.5.13 ima_tx_grp n _stat_ctl (transmit gro up status and control) this register contains the value of the group status and control field for the transmitted icp cells. group 1?16 address n =1 n =2 n =3 n =4 n =5 n =6 n =7 n =8 n =9 n =10 n =11 n =12 n =13 n =14 n =15 n =16 0x824 0x82c 0x834 0x83c 0x924 0x92c 0x934 0x93c 0xa2 4 0xa2c 0xa3 4 0xa3c 0xb2 4 0xb2c 0xb3 4 0xb3c m28525 m28529 group 17?32 address n =17 n =18 n =19 n =20 n =21 n =22 n =23 n =24 n =25 n =26 n =27 n =28 n =29 n =30 n =31 n =32 0xc2 4 0xc2 c 0xc3 4 0xc3 c 0xca 4 0xca c 0xcb 4 0xcb c 0xd2 4 0xd2 c 0xd3 4 0xd3 c 0xda 4 0xda c 0xdb 4 0xdb c m28525 -- not applicable m28529 bit default name description 7?4 0x00 group state 0 = start-up 1 = start-up-ack 2 = config-abort?unsupported m 3 = config-abort?incompatible symmetry 4 = config-abort?unsupported ima version 5?7 = reserved for other config-abort states 8 = insufficient links 9 = blocked 0xa = operational 0xb?f = reserved 3?2 0 group symmetry 0 = symmetrical configuration and operation 1 = symmetrical configurati on and asymmetrical operation 2 = asymmetrical configuration and operation 3 = alternate symmetrical configuration and operation 1?0 0 frame length (m) 0 = m is 32 1 = m is 64 2 = m is 128 3 = m is 256
registers 28529-dsh-001-k mindspeed technologies ? 213 mindspeed proprietary and confidential 2.5.14 ima_tx_grp n _timing_info (transmit timing information) this register contains the value of the transmit timing information field for the transmitted icp cells. group 1?16 address n =1 n =2 n =3 n =4 n =5 n =6 n =7 n =8 n =9 n =10 n =11 n =12 n =13 n =14 n =15 n =16 0x82 5 0x82d 0x83 5 0x83d 0x92 5 0x92d 0x93 5 0x93d 0xa2 5 0xa2d 0xa3 5 0xa3d 0xb2 5 0xb2d 0xb3 5 0xb3d m28525 m28529 group 17?32 address n =17 n =18 n =19 n =20 n =21 n =22 n =23 n =24 n =25 n =26 n =27 n =28 n =29 n =30 n =31 n =32 0xc25 0xc2 d 0xc35 0xc3 d 0xca 5 0xca d 0xcb 5 0xcb d 0xd2 5 0xd2 d 0xd3 5 0xd3 d 0xda 5 0xda d 0xdb 5 0xdb d m28525 -- not applicable m28529 bit default name description 7 0 unused: set to 0. 6 0 unused: set to 0. 5 0 tx clock mode 0 = independent transmit clock (itc) 1 = common transmit clock (ctc) 4?0 0 timing reference link id this field contains the lid of the transmit trl. range: 0x0?0x1f
registers 28529-dsh-001-k mindspeed technologies ? 214 mindspeed proprietary and confidential 2.5.15 ima_tx_grp n _test_ctl (transmit test control) this register contains the value of the tx test control field for the transmitted icp cells. group 1?16 address n =1 n =2 n =3 n =4 n =5 n =6 n =7 n =8 n =9 n =10 n =11 n =12 n =13 n =14 n =15 n =16 0x826 0x82e 0x836 0x83e 0x926 0x92e 0x936 0x93e 0xa2 6 0xa2e 0xa3 6 0xa3e 0xb2 6 0xb2e 0xb3 6 0xb3e m28525 m28529 group 17?32 address n =17 n =18 n =19 n =20 n =21 n =22 n =23 n =24 n =25 n =26 n =27 n =28 n =29 n =30 n =31 n =32 0xc26 0xc2e 0xc36 0xc3e 0xca 6 0xca e 0xcb 6 0xcb e 0xd2 6 0xd2 e 0xd3 6 0xd3 e 0xda 6 0xda e 0xdb 6 0xdb e m28525 -- not applicable m28529 bit default name description 7 0 unused: set to 0. 6 0 unused: set to 0. 5 0 test link command 0 = inactive 1 = active 4?0 0 test link id this field contains the lid of the transmit test link. range: 0x0?0x1f
registers 28529-dsh-001-k mindspeed technologies ? 215 mindspeed proprietary and confidential 2.5.16 ima_tx_grp n _tx_test_pattern (transmit group tx test pattern) this register contains the value of the tx test pattern field for the transmitted icp cells. group 1?16 address n =1 n =2 n =3 n =4 n =5 n =6 n =7 n =8 n =9 n =10 n =11 n =12 n =13 n =14 n =15 n =16 0x827 0x82f 0x837 0x83f 0x927 0x92f 0x937 0x93f 0xa27 0xa2f 0xa37 0xa3f 0xb27 0xb2f 0xb37 0xb3f m28525 m28529 group 17?32 address n =17 n =18 n =19 n =20 n =21 n =22 n =23 n =24 n =25 n =26 n =27 n =28 n =29 n =30 n =31 n =32 0xc27 0xc2f 0xc37 0xc3f 0xca 7 0xcaf 0xcb 7 0xcbf 0xd2 7 0xd2f 0xd3 7 0xd3f 0xda 7 0xda f 0xdb 7 0xdb f m28525 -- not applicable m28529 bit default name description 7?0 0x0 tx test pattern if the test link command is set to ac tive, the tx test pattern is sent in the icp cell of the transmit test link. for other links and when th e test link command is inactive, the tx test pattern in the transmit icp cells will au tomatically be set to 0x00. range: 0x00?0xff
registers 28529-dsh-001-k mindspeed technologies ? 216 mindspeed proprietary and confidential 2.5.17 ima_tx_atm n _cell_count_lsb (trans mit cell count lsbs) this register contains the least significant bits of a 16 bit count of the number of atm layer cells transmitted over the transmit atm side utopia bus for a particular utopia address. the register is read only. tx utopia address 0 - 15 n =0 n =1 n =2 n =3 n =4 n =5 n =6 n =7 n =8 n =9 n =10 n =11 n =12 n =13 n =14 n =15 0x840 0x842 0x844 0x846 0x940 0x942 0x944 0x946 0xa40 0xa42 0xa44 0xa46 0xb40 0xb42 0xb44 0xb46 m28525 m28529 tx utopia address 16?31 n =16 n =17 n =18 n =19 n =20 n =21 n =22 n =23 n =24 n =25 n =26 n =27 n =28 n =29 n =30 n =31 0xc40 0xc42 0xc44 0xc46 0xcc 0 0xcc 2 0xcc 4 0xcc 6 0xd4 0 0xd4 2 0xd4 4 0xd4 6 0xdc 0 0xdc 2 0xdc 4 0xdc 6 m28525 -- not applicable m28529 bit default name description 7-0 0 transmit cell count lsbs transmit cell count: this field contains the least signif icant bits of a 16-bit count of the number of atm layer cells transmitted over the specific utopia address. a write operation with data = 0x01 to the first address (0x840 for address 0, 0x842 for address 1, etc.) transfers the state of all 16 bits of the counter to registers that are accessible to the microprocessor bus and clears the state of the counter, the first address should be read first. the second address (0x841 for address 0, 0x843 for address 1, etc.) is read next. a write operation with data = 0x00 to the first address of each group returns back to the raw counters.
registers 28529-dsh-001-k mindspeed technologies ? 217 mindspeed proprietary and confidential 2.5.18 ima_tx_atm n _cell_count_msb (trans mit cell count msbs) this register contains the most significant bits of a 16 bit count of the number of atm layer cells transmitted over the transmit atm side utopia bus for a particular utopia address. the register is read only. tx utopia address 0 - 15 n =0 n =1 n =2 n =3 n =4 n =5 n =6 n =7 n =8 n =9 n =10 n =11 n =12 n =13 n =14 n =15 0x841 0x843 0x845 0x847 0x941 0x943 0x945 0x947 0xa41 0xa43 0xa45 0xa47 0xb41 0xb43 0xb45 0xb47 m28525 m28529 tx utopia address 16?31 n =16 n =17 n =18 n =19 n =20 n =21 n =22 n =23 n =24 n =25 n =26 n =27 n =28 n =29 n =30 n =31 0xc41 0xc43 0xc45 0xc47 0xcc 1 0xcc 3 0xcc 5 0xcc 7 0xd4 1 0xd4 3 0xd4 5 0xd4 7 0xdc 1 0xdc 3 0xdc 5 0xdc 7 m28525 -- not applicable m28529 bit default name description 7-0 0 transmit cell count msbs transmit cell count : this field contains the most signif icant bits of a 16 bit count of the number of atm layer cells transmitted o ver the specific utop ia address. a write operation with data = 0x01 to the first a ddress (0x840 for address 0, 0x842 for address 1, etc.) transfers the state of all 16 bits of the counter to registers that are accessible to the microprocessor bus and clears the counter. a read operation should then be performed to read the previous state of th e counter. the first address should be read first. the second address (0x841 for address 0, 0x843 for address 1, etc.) is read next. a write operation with data = 0x00 to the first address of each group returns back to the raw counters.
registers 28529-dsh-001-k mindspeed technologies ? 218 mindspeed proprietary and confidential 2.5.19 ima_rx_atm n _cell_count_lsb (receive cell count lsbs) this register contains the least significant bits of a 16 bit count of the number of atm layer cells received over the receive atm side utopia bus for a particular utopia address. the register is read only. rx utopia address 0 - 15 n =0 n =1 n =2 n =3 n =4 n =5 n =6 n =7 n =8 n =9 n =10 n =11 n =12 n =13 n =14 n =15 0x850 0x852 0x854 0x856 0x950 0x952 0x954 0x956 0xa50 0xa52 0xa54 0xa56 0xb50 0xb52 0xb54 0xb56 m28525 m28529 rx utopia address 16?31 n =16 n =17 n =18 n =19 n =20 n =21 n =22 n =23 n =24 n =25 n =26 n =27 n =28 n =29 n =30 n =31 0xc48 0xc4 a 0xc4 c 0xc4e 0xcc 8 0xcc a 0xcc c 0xcc e 0xd4 8 0xd4 a 0xd4 c 0xd4 e 0xdc 8 0xdc a 0xdc c 0xdc e m28525 -- not applicable m28529 bit default name description 7-0 0 receive cell count lsbs receive cell count : this field contains the least significant bits of a 16 bit count of the number of atm layer cells received over the specific utopia address. a write operation with data = 0x01 to the first address (0x 850 for address 0, 0x852 for address 1, etc.) transfers the state of all 16 bits of the co unter to registers that are accessible to the microprocessor bus and clears the counter. a read operation should then be performed to read the previous state of the counter. the fi rst address should be read first. the second address (0x851 for address 0, 0x853 for address 1, etc.) is read next. a write operation with data = 0x00 to the first address of each group returns back to the raw counters.
registers 28529-dsh-001-k mindspeed technologies ? 219 mindspeed proprietary and confidential 2.5.20 ima_rx_atm n _cell_count_msb (receive cell count msbs) this register contains the most significant bits of a 16 bi t count of the number of atm layer cells received over the receive atm side utopia bus for a particular utopia address. the register is read only. rx utopia address 0 - 15 n =0 n =1 n =2 n =3 n =4 n =5 n =6 n =7 n =8 n =9 n =10 n =11 n =12 n =13 n =14 n =15 0x851 0x853 0x855 0x857 0x951 0x953 0x955 0x957 0xa51 0xa53 0xa55 0xa57 0xb51 0xb53 0xb55 0xb57 m28525 m28529 rx utopia address 16?31 n =16 n =17 n =18 n =19 n =20 n =21 n =22 n =23 n =24 n =25 n =26 n =27 n =28 n =29 n =30 n =31 0xc49 0xc4 b 0xc4 d 0xc4f 0xcc 9 0xcc b 0xcc d 0xccf 0xd4 9 0xd4 b 0xd4 d 0xd4f 0xdc 9 0xdc b 0xdc d 0xdc f m28525 -- not applicable m28529 bit default name description 7-0 0 receive cell count msbs receive cell count : this field contains the most significant bits of a 16 bit count of the number of atm layer cells r eceived over the specific utopia address. a write operation with data = 0x01 to the first address (0x850 for address 0, 0x852 for address 1, etc.) transfers the state of all 16 bits of the counter to regi sters that are accessible to the microprocessor bus and clears the counter. a read operation should then be performed to read the previous state of the counter. the first address should be read first. the second address (0x851 for address 0, 0x853 for address 1, etc.) is read next. a write operation with data = 0x00 to the first address of each group returns back to the raw counters.
registers 28529-dsh-001-k mindspeed technologies ? 220 mindspeed proprietary and confidential 2.5.21 ima_rx_grp n _cfg (receive group status and control) this register, in conjunction with the ima_rx_grp n _ctl and ima_rx_grp n _first_phy_addr registers, controls the operation of the receive ima group. group 1?16 address n =1 n =2 n =3 n =4 n =5 n =6 n =7 n =8 n =9 n =10 n =11 n =12 n =13 n =14 n =15 n =16 0x8d 0 0x8d 4 0x8d 8 0x8d c 0x9d 0 0x9d 4 0x9d 8 0x9d c 0xad 0 0xad 4 0xad 8 0xad c 0xbd 0 0xbd 4 0xbd 8 0xbd c m28525 m28529 group 17?32 address n =17 n =18 n =19 n =20 n =21 n =22 n =23 n =24 n =25 n =26 n =27 n =28 n =29 n =30 n =31 n =32 0xc50 0xc54 0xc58 0xc5 c 0xcd 0 0xcd 4 0xcd 8 0xcd c 0xd5 0 0xd5 4 0xd5 8 0xd5 c 0xdd 0 0xdd 4 0xdd 8 0xdd c m28525 -- not applicable m28529 bit default name description 7 0 check group id 1 = the receive group id is compared wi th the expected group id as part of link framing 0 = the receive group id is ignored 6 0 acquire frame length 1 = the frame length and ima version acquired from the received link is used as part of link framing 0 = the frame length and ima version from the r eceived link is compared against the expected frame length and ima version as part of link framing 5?4 0 maximum differential delay reserved. set to 0. 3?2 0 group symmetry 0 = symmetrical configuration and operation 1 = symmetrical configuration and asymmetrical operation 2 = asymmetrical configuration and operation 3 = alternate symmetrical configuration and operation 1?0 0 frame length (m) 0 = m is 32 1 = m is 64 2 = m is 128 3 = m is 256
registers 28529-dsh-001-k mindspeed technologies ? 221 mindspeed proprietary and confidential 2.5.22 ima_rx_grp n _ctl (receive group control register) this register, in conjunction with the ima_rx_grp n _cfg and ima_rx_grp n _first_phy_addr registers, controls the operation of the receive ima group. group 1?16 address n =1 n =2 n =3 n =4 n =5 n =6 n =7 n =8 n =9 n =10 n =11 n =12 n =13 n =14 n =15 n =16 0x8d 1 0x8d 5 0x8d 9 0x8dd 0x9d 1 0x9d 5 0x9d 9 0x9dd 0xad 1 0xad 5 0xad 9 0xad d 0xbd 1 0xbd 5 0xbd 9 0xbd d m28525 m28529 group 17?32 address n =17 n =18 n =19 n =20 n =21 n =22 n =23 n =24 n =25 n =26 n =27 n =28 n =29 n =30 n =31 n =32 0xc5 1 0xc5 5 0xc5 9 0xc5 d 0xcd 1 0xcd 5 0xcd 9 0xcd d 0xd5 1 0xd5 5 0xd5 9 0xd5 d 0xdd 1 0xdd 5 0xdd 9 0xdd d m28525 -- not applicable m28529 bit default name description 7 0 group enable 1 = group is established and a round-robin is created 0 = group is not established 6 0 sw timeout expired 1 = certain lsm transitions (usable active) are allowed 0 = certain lsm transitions (usable active) are blocked 5 ? ? reserved. set to 0. 4?0 0x0 group size sets the number of configured links within group. range: 0x0?0x1f (1?32 links in group)
registers 28529-dsh-001-k mindspeed technologies ? 222 mindspeed proprietary and confidential 2.5.23 ima_rx_grp n _first_phy_addr (recei ve first phy address) this register, in conjunction with the ima_rx_grp n _ctl and ima_rx_grp n _cfg registers, controls the operation of the receive ima group. group 1?16 address n =1 n =2 n =3 n =4 n =5 n =6 n =7 n =8 n =9 n =10 n =11 n =12 n =13 n =14 n =15 n =16 0x8d 2 0x8d 6 0x8da 0x8de 0x9d 2 0x9d 6 0x9da 0x9de 0xad 2 0xad 6 0xada 0xad e 0xbd 2 0xbd 6 0xbda 0xbd e m28525 m28529 group 17?32 address n =17 n =18 n =19 n =20 n =21 n =22 n =23 n =24 n =25 n =26 n =27 n =28 n =29 n =30 n =31 n =32 0xc5 2 0xc5 6 0xc5 a 0xc5e 0xcd 2 0xcd 6 0xcd a 0xcd e 0xd5 2 0xd5 6 0xd5 a 0xd5e 0xdd 2 0xdd 6 0xdd a 0xdd e m28525 -- not applicable m28529 bit default name description 7 0 resync group 1 = enables the link di fferential delay synchronization process 0 = disables the link differential delay synchronization process 6 0 drain buffer this bit is used by the software driv er to reset the differen tial delay in t1/e1 mode: 1 = allows the differential delay buffer to drain excess cell buffering. 0 = normal delay buffering. 5 0 rx ima version ima oam label value 1 = ima v1.1 0 = ima v1.0 4?0 0x00 link phy address this fiel d contains the phy port addres s of the receive link with the lowest lid in the group. m28525: range: 0?0xf m28529: range: 0?0x1f
registers 28529-dsh-001-k mindspeed technologies ? 223 mindspeed proprietary and confidential 2.5.24 ima_rx_grp n _id (expected receive group id) this register contains the value of the expected ima group id field for the received icp cells. group 1?16 address n =1 n =2 n =3 n =4 n =5 n =6 n =7 n =8 n =9 n =10 n =11 n =12 n =13 n =14 n =15 n =16 0x8d 3 0x8d 7 0x8db 0x8df 0x9d 3 0x9d 7 0x9db 0x9df 0xad 3 0xad 7 0xad b 0xad f 0xbd 3 0xbd 7 0xbd b 0xbd f m28525 m28529 group 17?32 address n =17 n =18 n =19 n =20 n =21 n =22 n =23 n =24 n =25 n =26 n =27 n =28 n =29 n =30 n =31 n =32 0xc5 3 0xc5 7 0xc5 b 0xc5f 0xcd 3 0xcd 7 0xcd b 0xcdf 0xd5 3 0xd5 7 0xd5 b 0xd5f 0xdd 3 0xdd 7 0xdd b 0xddf m28525 -- not applicable m28529 bit default name description 7?0 0x00 expected rx group id this field contains the group id expected in the receive icp cells of all links in this group. range : 0x00?0xff
registers 28529-dsh-001-k mindspeed technologies ? 224 mindspeed proprietary and confidential 2.5.25 ima_rx_grp n _rx_test_pattern (receive group rx test pattern) this read-only register contains the value of the rx test pattern field acquired from the received icp cells. group 1?16 address n =1 n =2 n =3 n =4 n =5 n =6 n =7 n =8 n =9 n =10 n =11 n =12 n =13 n =14 n =15 n =16 0x8e0 0x8e8 0x8f0 0x8f8 0x9e0 0x9e8 0x9f0 0x9f8 0xae0 0xae8 0xaf0 0xaf8 0xbe0 0xbe8 0xbf0 0xbf8 m28525 m28529 group 17?32 address n =17 n =18 n =19 n =20 n =21 n =22 n =23 n =24 n =25 n =26 n =27 n =28 n =29 n =30 n =31 n =32 0xc6 0 0xc6 8 0xc7 0 0xc78 0xce0 0xce8 0xcf0 0xcf8 0xd6 0 0xd6 8 0xd70 0xd78 0xde0 0xde8 0xdf0 0xdf8 m28525 -- not applicable m28529 bit default name description 7?0 ? rx test pattern this field reflects the value of the rx test pattern byte acquired from the receive side test link. range: 0x00?0xff
registers 28529-dsh-001-k mindspeed technologies ? 225 mindspeed proprietary and confidential 2.5.26 ima_rx_grp n _stat_ctl_change (receive group status & control change indication) this read-only register contains the value of the status and control indication field acquired from the received icp cells. group 1?16 address n =1 n =2 n =3 n =4 n =5 n =6 n =7 n =8 n =9 n =10 n =11 n =12 n =13 n =14 n =15 n =16 0x8e2 0x8ea 0x8f 2 0x8fa 0x9e2 0x9ea 0x9f 2 0x9fa 0xae 2 0xaea 0xaf 2 0xafa 0xbe 2 0xbea 0xbf 2 0xbfa m28525 m28529 group 17?32 address n =17 n =18 n =19 n =20 n =21 n =22 n =23 n =24 n =25 n =26 n =27 n =28 n =29 n =30 n =31 n =32 0xc6 2 0xc6 a 0xc7 2 0xc7a 0xce2 0xcea 0xcf2 0xcfa 0xd6 2 0xd6 a 0xd72 0xd7 a 0xde2 0xde a 0xdf2 0xdfa m28525 -- not applicable m28529 bit default name description 7?0 ? rx scci this field reflects the value of the status & change control indication byte acquired from the receive icp cells of the monitored link. range: 0x00?0xff
registers 28529-dsh-001-k mindspeed technologies ? 226 mindspeed proprietary and confidential 2.5.27 ima_rx_grp n _actual_grp_id (actual receive group id) this read-only register contains the value of the ima id field acquired from the received icp cells. group 1?16 address n =1 n =2 n =3 n =4 n =5 n =6 n =7 n =8 n =9 n =10 n =11 n =12 n =13 n =14 n =15 n =16 0x8e3 0x8eb 0x8f 3 0x8fb 0x9e3 0x9eb 0x9f 3 0x9fb 0xae3 0xaeb 0xaf 3 0xafb 0xbe3 0xbeb 0xbf 3 0xbfb m28525 m28529 group 17?32 address n =17 n =18 n =19 n =20 n =21 n =22 n =23 n =24 n =25 n =26 n =27 n =28 n =29 n =30 n =31 n =32 0xc6 3 0xc6 b 0xc7 3 0xc7b 0xce3 0xceb 0xcf3 0xcfb 0xd6 3 0xd6 b 0xd73 0xd7 b 0xde3 0xde b 0xdf3 0xdfb m28525 -- not applicable m28529 bit default name description 7?0 ? actual rx group id this field contains the group id acquire d from the receive icp cells of the monitored link. range: 0x00?0xff
registers 28529-dsh-001-k mindspeed technologies ? 227 mindspeed proprietary and confidential 2.5.28 ima_rx_grp n _stat_ctl (receive group status and control) this read-only register contains the value of the group status and control field acquired from the received icp cells. group 1?16 address n =1 n =2 n =3 n =4 n =5 n =6 n =7 n =8 n =9 n =10 n =11 n =12 n =13 n =14 n =15 n =16 0x8e4 0x8ec 0x8f 4 0x8fc 0x9e4 0x9ec 0x9f 4 0x9fc 0xae4 0xaec 0xaf 4 0xafc 0xbe4 0xbec 0xbf 4 0xbfc m28525 m28529 group 17?32 address n =17 n =18 n =19 n =20 n =21 n =22 n =23 n =24 n =25 n =26 n =27 n =28 n =29 n =30 n =31 n =32 0xc6 4 0xc6 c 0xc7 4 0xc7c 0xce4 0xcec 0xcf4 0xcfc 0xd6 4 0xd6 c 0xd74 0xd7 c 0xde4 0xde c 0xdf4 0xdfc m28525 -- not applicable m28529 bit default name description 7?4 ? group state 0 = start-up 1 = start-up-ack 2 = config-abort?unsupported m 3 = config-abort?incompatible symmetry 4 = config-abort?unsupported ima version 5?7 = reserved for other config-abort states 8 = insufficient links 9 = blocked 0xa = operational 0xb?f = reserved 3?2 ? group symmetry 0 = symmetrical configuration and operation 1 = symmetrical configuration and asymmetrical operation 2 = asymmetrical configuration and operation 1?0 ? frame length (m) 0 = m is 32 1 = m is 64 2 = m is 128 3 = m is 256
registers 28529-dsh-001-k mindspeed technologies ? 228 mindspeed proprietary and confidential 2.5.29 ima_rx_grp n _timing_info (receive timing information) this read-only register contains the value of the transmit timing information field acquired from the received icp cells. group 1?16 address n =1 n =2 n =3 n =4 n =5 n =6 n =7 n =8 n =9 n =10 n =11 n =12 n =13 n =14 n =15 n =16 0x8e5 0x8ed 0x8f 5 0x8fd 0x9e5 0x9ed 0x9f 5 0x9fd 0xae 5 0xaed 0xaf 5 0xafd 0xbe 5 0xbed 0xbf 5 0xbfd m28525 m28529 group 17?32 address n =17 n =18 n =19 n =20 n =21 n =22 n =23 n =24 n =25 n =26 n =27 n =28 n =29 n =30 n =31 n =32 0xc6 5 0xc6 d 0xc7 5 0xc7 d 0xce5 0xce d 0xcf5 0xcfd 0xd6 5 0xd6 d 0xd7 5 0xd7 d 0xde 5 0xde d 0xdf5 0xdfd m28525 -- not applicable m28529 bit default name description 7 ? ? unused 6 ? ? unused 5 ? rx clock mode 0 = independent transmit clock (itc) 1 = common transmit clock (ctc) 4?0 ? timing reference link id this field contains the lid of the receive trl. range: 0x0?0x1f
registers 28529-dsh-001-k mindspeed technologies ? 229 mindspeed proprietary and confidential 2.5.30 ima_rx_grp n _test_ctl (receive test control) this read-only register contains the value of the tx test control field acquired from the received icp cells. group 1?16 address n =1 n =2 n =3 n =4 n =5 n =6 n =7 n =8 n =9 n =10 n =11 n =12 n =13 n =14 n =15 n =16 0x8e6 0x8ee 0x8f6 0x8fe 0x9e6 0x9ee 0x9f6 0x9fe 0xae6 0xaee 0xaf 6 0xafe 0xbe6 0xbee 0xbf 6 0xbfe m28525 m28529 group 17?32 address n =17 n =18 n =19 n =20 n =21 n =22 n =23 n =24 n =25 n =26 n =27 n =28 n =29 n =30 n =31 n =32 0xc6 6 0xc6e 0xc7 6 0xc7e 0xce6 0xcee 0xcf6 0xcfe 0xd6 6 0xd6 e 0xd7 6 0xd7 e 0xde 6 0xde e 0xdf6 0xdfe m28525 -- not applicable m28529 bit default name description 7 ? ? unused 6 ? ? unused 5 ? test link command 0 = inactive 1 = active 4?0 ? test link id this field contains the lid of the receive test link. range: 0x0?0x1f
registers 28529-dsh-001-k mindspeed technologies ? 230 mindspeed proprietary and confidential 2.5.31 ima_rx_grp n _tx_test_pattern (receive group tx test pattern) this read-only register contains the value of the tx test pattern field acquired from the received icp cells. 2.6 ima link registers the ima link layer contains configuration and status information that is associated with ima groups or pass- through facilities. 2.6.1 0x81e?ima_lnk_sem (lin k table control register) for the following bits, 1 = the link table is being updated, 0 = the link table is not being updated. the update enable must be set to 1 prior to writing the link table. all elements of the link table must be re-written. after writing to all 8 elements, the update enable is reset to 0. the link tables are described below. group 1?16 address n =1 n =2 n =3 n =4 n =5 n =6 n =7 n =8 n =9 n =10 n =11 n =12 n =13 n =14 n =15 n =16 0x8e7 0x8ef 0x8f7 0x8ff 0x9e7 0x9ef 0x9f7 0x9ff 0xae7 0xaef 0xaf7 0xaff 0xbe7 0xbef 0xbf7 0xbff m28525 m28529 group 17?32 address n =17 n =18 n =19 n =20 n =21 n =22 n =23 n =24 n =25 n =26 n =27 n =28 n =29 n =30 n =31 n =32 0xc6 7 0xc6f 0xc7 7 0xc7f 0xce7 0xcef 0xcf7 0xcff 0xd6 7 0xd6f 0xd7 7 0xd7f 0xde 7 0xdef 0xdf7 0xdff m28525 -- not applicable m28529 bit default name description 7?0 ? tx test pattern if the test link command is set to acti ve, the tx test pattern is accessed from the icp cell of the transmit test link. this register should be read multiple times (debounced) to ensure receipt of a valid test pattern. range: 0x00?0xff note: this register cannot be read back. bit default name description 7 0 update enable for receive facilities 24?31 addresses 0xb80?0xb87, 0xba8?0xbaf (not defined for m28525) 6 0 update enable for receive facilities 16?23 addresses 0xa80?0xa87, 0xaa8?0xaaf (not defined for m28525)
registers 28529-dsh-001-k mindspeed technologies ? 231 mindspeed proprietary and confidential 5 0 update enable for receive facilities 8?15 addresses 0x980?0x987, 0x9a8?0x9af (not defined for m28525) 4 0 update enable for receive facilities 0?7 addresses 0x880?0x887, 0x8a8?0x8af (not defined for m28525) 3 0 update enable for transmit facilities 24?31 addresses 0xb60?0xb67, 0xb70?0xb77 (not defined for m28525) 2 0 update enable for transmit facilities 16?23 addresses 0xa60?0xa67, 0xa70?0xa77 (not defined for m28525) 1 0 update enable for transmit facilities 8?15 addresses 0x960?0x967, 0x970?0x977 (not defined for m28525) 0 0 update enable for transmit facilities 0?7 addresses 0x860?0x867, 0x870?0x877 bit default name description
registers 28529-dsh-001-k mindspeed technologies ? 232 mindspeed proprietary and confidential 2.6.2 ima_tx_lnk n _ctl (transmit link control register) this register, in conjunction with ima_tx_lnk n _id register, configures the ima link attributes for the transmit port. hex address n address n address 0 0x860 16 0xa60 1 0x861 17 0xa61 2 0x862 18 0xa62 3 0x863 19 0xa63 4 0x864 20 0xa64 5 0x865 21 0xa65 6 0x866 22 0xa66 7 0x867 23 0xa67 8 0x960 24 0xb60 9 0x961 25 0xb61 10 0x962 26 0xb62 11 0x963 27 0xb63 12 0x964 28 0xb64 13 0x965 29 0xb65 14 0x966 30 0xb66 15 0x967 31 0xb67 bit default name description 7 0 link assigned 1 = facility is part of ima group 0 = facility is a bypass channel (pass-through or unassigned) 6 0 link inhibit 1 = link is blocked from use 0 = link is not inhibited 5 0 link fault 1 = link fault failure is active 0 = link fault failure is inactive 4?0 0 next link phy address this field contains the phy address of the next link in the ima group. if the link is a pass- through facility, this field is ignored but is re commended to be set to the phy address of the pass-through facility (i.e., set to 0 for phy address 0, set to 1 for phy address 1, etc.). m28525: range: 0?0x0f m28529: range: 0?0x1f
registers 28529-dsh-001-k mindspeed technologies ? 233 mindspeed proprietary and confidential 2.6.3 ima_tx_lnk n _state (transmit link status register) this read-only register provides state and status information for the transmit link. hex address n address n address 0 0x868 16 0xa68 1 0x869 17 0xa69 2 0x86a 18 0xa6a 3 0x86b 19 0xa6b 4 0x86c 20 0xa6c 5 0x86d 21 0xa6d 6 0x86e 22 0xa6e 7 0x86f 23 0xa6f 8 0x968 24 0xb68 9 0x969 25 0xb69 10 0x96a 26 0xb6a 11 0x96b 27 0xb6b 12 0x96c 28 0xb6c 13 0x96d 29 0xb6d 14 0x96e 30 0xb6e 15 0x96f 31 0xb6f bit default name description 7?6 ? tx-stuff-ima counter this field contains a count of the num ber of near-end transmit cell stuffing events. upon a read of this address, the contents of the counter is transferred to a register that is accessible to the microprocessor bus and the counter is cleared. 5 ? ? reserved. 4 ? ? reserved. 3 ? waiting for sw timer 1 = a transition of the tran smit lsm is waiting for an enable from software 0 = no transition of the lsm is waiting for software 2?0 ? ne tx lsm state 0 = not in group 1 = unusable?no reason given 2 = unusable?fault 3 = unusable?mis-connected 4 = unusable?blocked 5 = unusable?failed 6 = usable 7 = active
registers 28529-dsh-001-k mindspeed technologies ? 234 mindspeed proprietary and confidential 2.6.4 ima_tx_lnk n _id (transmit link id register) this register, in conjunction with ima_tx_lnk n _ctl register, configures the ima link attributes for the transmit port. hex address n address n address 0 0x870 16 0xa70 1 0x871 17 0xa71 2 0x872 18 0xa72 3 0x873 19 0xa73 4 0x874 20 0xa74 5 0x875 21 0xa75 6 0x876 22 0xa76 7 0x877 23 0xa77 8 0x970 24 0xb70 9 0x971 25 0xb71 10 0x972 26 0xb72 11 0x973 27 0xb73 12 0x974 28 0xb74 13 0x975 29 0xb75 14 0x976 30 0xb76 15 0x977 31 0xb77 bit default name description 7 ? ? reserved. set to 0 6 ? ? reserved. set to 0 5 0 link misconnect 1 = link misconnect failure is active 0 = link misconnect failure is inactive 4?0 0x00 link id this field contains the tran smit link id assigned to this facility. range: 0x00?0x1f
registers 28529-dsh-001-k mindspeed technologies ? 235 mindspeed proprietary and confidential 2.6.5 ima_rx_lnk n _ctl (receive link control register) this register, in conjunction with ima_rx_lnk n _id register, configures the ima link attributes for the receive port. hex address n address n address 0 0x880 16 0xa80 1 0x881 17 0xa81 2 0x882 18 0xa82 3 0x883 19 0xa83 4 0x884 20 0xa84 5 0x885 21 0xa85 6 0x886 22 0xa86 7 0x887 23 0xa87 8 0x980 24 0xb80 9 0x981 25 0xb81 10 0x982 26 0xb82 11 0x983 27 0xb83 12 0x984 28 0xb84 13 0x985 29 0xb85 14 0x986 30 0xb86 15 0x987 31 0xb87 bit default name description 7 0 link assigned 1 = facility is part of ima group 0 = facility is a bypass channel (pass-through or unassigned) 6?5 0 link state 0 = link is not inhibited 1 = link fault failure is active 2 = link is blocked from use 3 = rx failed condition 4?0 0 next link phy address this field contains the phy address of the next link in the ima group. if the link is a pass- through facility, this field is ignored but is re commended to be set to the phy address of the pass-through facility (i.e., set to 0 for phy address 0, set to 1 for phy address 1, etc.). m28525: range: 0?f m28529: range: 0?0x1f
registers 28529-dsh-001-k mindspeed technologies ? 236 mindspeed proprietary and confidential 2.6.6 ima_rx_lnk n _state (receive link status register) this read-only register provides state and status information for the receive link. hex address n address n address 0 0x888 16 0xa88 1 0x889 17 0xa89 2 0x88a 18 0xa8a 3 0x88b 19 0xa8b 4 0x88c 20 0xa8c 5 0x88d 21 0xa8d 6 0x88e 22 0xa8e 7 0x88f 23 0xa8f 8 0x988 24 0xb88 9 0x989 25 0xb89 10 0x98a 26 0xb8a 11 0x98b 27 0xb8b 12 0x98c 28 0xb8c 13 0x98d 29 0xb8d 14 0x98e 30 0xb8e 15 0x98f 31 0xb8f bit default name description 7?6 ? rx-stuff-ima counter this field contains a count of the number of near-end receive cel l stuffing events. upon a read of this address, the contents of the counter is transferred to a register that is accessible to the microprocessor bus and the counter is cleared. 5 ? ? reserved. 4 ? ? reserved. 3 ? waiting for sw timer 1 = a transition of the r eceive lsm is waiting for an enable from software 0 = no transition of the lsm is waiting for software 2?0 ? ne rx lsm state 0 = not in group 1 = unusable?no reason given 2 = unusable?fault 3 = unusable?mis-connected 4 = unusable?blocked 5 = unusable?failed 6 = usable 7 = active
registers 28529-dsh-001-k mindspeed technologies ? 237 mindspeed proprietary and confidential 2.6.7 ima_rx_lnk n _defect (receive link defects register) this register provides state and status information for the receive link. this register is primarily read-only except for bit 1 which is read/write. hex address n address n address 0 0x890 16 0xa90 1 0x891 17 0xa91 2 0x892 18 0xa92 3 0x893 19 0xa93 4 0x894 20 0xa94 5 0x895 21 0xa95 6 0x896 22 0xa96 7 0x897 23 0xa97 8 0x990 24 0xb90 9 0x991 25 0xb91 10 0x992 26 0xb92 11 0x993 27 0xb93 12 0x994 28 0xb94 13 0x995 29 0xb95 14 0x996 30 0xb96 15 0x997 31 0xb97 bit default name description 7? ? (lif defect) 1 = the lif defect has changed st ate since the last time this register was read 0 = the lif defect has not changed state 6 ? lif defect 1 = the lif defect is currently active 0 = the lif defect is inactive 5? ? (lods defect) 1 = the lods defect has changed st ate since the last time this register was read 0 = the lods defect has not changed state 4 ? lods defect 1 = the lods defect is currently active 0 = the lods defect is inactive 3? ? (rdi defect) 1 = the rdi defect has changed st ate since the last time this register was read 0 = the rdi defect h as not changed state 2 ? rdi defect 1 = the rdi de fect is currently active 0 = the rdi defect is inactive 1 0 phy defect 1 = a phy defect is active 0 = all phy defects are inactive 0 ? rx_trl error this bit is set high if the transition detector for the rx_trl input detects a bad signal. this bit is active high and is reset upon reading this address.
registers 28529-dsh-001-k mindspeed technologies ? 238 mindspeed proprietary and confidential 2.6.8 ima_fe_tx_lnk n _cfg (fe transmit configuration register) this read-only register provides far-end transmit configuration information for the receive link. hex address n address n address 0 0x898 16 0xa98 1 0x899 17 0xa99 2 0x89a 18 0xa9a 3 0x89b 19 0xa9b 4 0x89c 20 0xa9c 5 0x89d 21 0xa9d 6 0x89e 22 0xa9e 7 0x89f 23 0xa9f 8 0x998 24 0xb98 9 0x999 25 0xb99 10 0x99a 26 0xb9a 11 0x99b 27 0xb9b 12 0x99c 28 0xb9c 13 0x99d 29 0xb9d 14 0x99e 30 0xb9e 15 0x99f 31 0xb9f bit default name description 7?6 ? frame length (m) this field contains the contents of the frame length field for the icp cell arriving on this facility. 0 = m is 32 1 = m is 64 2 = m is 128 3 = m is 256 5 ? ima version (ima oam label value) 1 = ima v1.1 0 = ima v1.0 4?0 ? link id this field contains the contents of the link id field for the icp cell arriving on this facility. range: 0x0?0x1f. note: the value in this register is undefined when there is no valid ima cell stream present on the link. the value in this register is also undefined for a maximum of two seconds following the creation of a group containing this link.
registers 28529-dsh-001-k mindspeed technologies ? 239 mindspeed proprietary and confidential 2.6.9 ima_fe_lnk n _state (fe link status register) this read-only register provides far-end link st atus information for the facility. hex address n address n address 0 0x8a0 16 0xaa0 1 0x8a1 17 0xaa1 2 0x8a2 18 0xaa2 3 0x8a3 19 0xaa3 4 0x8a4 20 0xaa4 5 0x8a5 21 0xaa5 6 0x8a6 22 0xaa6 7 0x8a7 23 0xaa7 8 0x9a0 24 0xba0 9 0x9a1 25 0xba1 10 0x9a2 26 0xba2 11 0x9a3 27 0xba3 12 0x9a4 28 0xba4 13 0x9a5 29 0xba5 14 0x9a6 30 0xba6 15 0x9a7 31 0xba7 bit default name description 7?5 ? fe tx lsm state 0 = not in group 1 = unusable?no reason given 2 = unusable?fault 3 = unusable?mis-connected 4 = unusable?blocked 5 = unusable?failed 6 = usable 7 = active 4?2 ? fe rx lsm state 0 = not in group 1 = unusable?no reason given 2 = unusable?fault 3 = unusable?mis-connected 4 = unusable?blocked 5 = unusable?failed 6 = usable 7 = active
registers 28529-dsh-001-k mindspeed technologies ? 240 mindspeed proprietary and confidential 2.6.10 ima_rx_lnk n _id (receive link id register) this register, in conjunction with ima_rx_lnk n _ctl register, configures the ima link attributes for the receive port. 1?0 ? fe rx defect indicator 0 = no defects 1 = physical link defect 2 = lif defect 3 = lods defect hex address n address n address 0 0x8a8 16 0xaa8 1 0x8a9 17 0xaa9 2 0x8aa 18 0xaaa 3 0x8ab 19 0xaab 4 0x8ac 20 0xaac 5 0x8ad 21 0xaad 6 0x8ae 22 0xaae 7 0x8af 23 0xaaf 8 0x9a8 24 0xba8 9 0x9a9 25 0xba9 10 0x9aa 26 0xbaa 11 0x9ab 27 0xbab 12 0x9ac 28 0xbac 13 0x9ad 29 0xbad 14 0x9ae 30 0xbae 15 0x9af 31 0xbaf bit default name description 7 ? ? reserved. set to 0 6 ? ? reserved. set to 0 5 0 link misconnect 1 = link misconnect failure is active 0 = link misconnect failure is inactive 4?0 0 link id this field contains the recei ve link id assigned to this facility. range: 0x00?0x1f bit default name description (continued)
registers 28529-dsh-001-k mindspeed technologies ? 241 mindspeed proprietary and confidential 2.6.11 ima_rx_lnk n _iv_cnt (ima violation counter register) this read-only register contains a count of the iv-ima anomalies for the receive link. hex address n address n address 0 0x8b0 16 0xab0 1 0x8b1 17 0xab1 2 0x8b2 18 0xab2 3 0x8b3 19 0xab3 4 0x8b4 20 0xab4 5 0x8b5 21 0xab5 6 0x8b6 22 0xab6 7 0x8b7 23 0xab7 8 0x9b0 24 0xbb0 9 0x9b1 25 0xbb1 10 0x9b2 26 0xbb2 11 0x9b3 27 0xbb3 12 0x9b4 28 0xbb4 13 0x9b5 29 0xbb5 14 0x9b6 30 0xbb6 15 0x9b7 31 0xbb7 bit default name description 7?0 ? iv-ima counter this field contains a count of the icp-er r, icp-inv, and icp-mis anomalies. writing a 0x01 to address 0x8b0 will freeze the val ue of all the iv-ima and oif-ima counters in the defined registers. the internal counters are cleared by th is action. after all the registers have been read, writing a 0x00 to address 0x8b0 will release the ?fr eeze? and the defined registers will reflect the current anomaly count.
registers 28529-dsh-001-k mindspeed technologies ? 242 mindspeed proprietary and confidential 2.6.12 ima_rx_lnk n _oif_cnt (out-of-ima fr ame counter register) this read-only register contains a count of the oif-ima anomalies for the receive link. hex address n address n address 0 0x8b8 16 0xab8 1 0x8b9 17 0xab9 2 0x8ba 18 0xaba 3 0x8bb 19 0xabb 4 0x8bc 20 0xabc 5 0x8bd 21 0xabd 6 0x8be 22 0xabe 7 0x8bf 23 0xabf 8 0x9b8 24 0xbb8 9 0x9b9 25 0xbb9 10 0x9ba 26 0xbba 11 0x9bb 27 0xbbb 12 0x9bc 28 0xbbc 13 0x9bd 29 0xbbd 14 0x9be 30 0xbbe 15 0x9bf 31 0xbbf bit default name description 7 ? ? reserved. 6 ? ? reserved. 5 ? ? reserved. 4 ? ? reserved. 3?0 ? oif-ima counter this field contains a count of the oif anomalies. writing a 0x01 to address 0x8b0 will freeze the value of all the iv-ima and oif-ima counters in the defined registers. the internal counters are cleared by this action. after all the registers h ave been read, writing a 0x00 to address 0x8b0 will release the ?freeze? and the defined register s will reflect the current anomaly count.
registers 28529-dsh-001-k mindspeed technologies ? 243 mindspeed proprietary and confidential 2.6.13 ima_fe_tx_lnk n _grp_id (fe transmit group id register) this read-only register contains the value of the ima id field acquired from the received icp for the receive link. hex address n address n address 0 0x8c0 16 0xac0 1 0x8c1 17 0xac1 2 0x8c2 18 0xac2 3 0x8c3 19 0xac3 4 0x8c4 20 0xac4 5 0x8c5 21 0xac5 6 0x8c6 22 0xac6 7 0x8c7 23 0xac7 8 0x9c0 24 0xbc0 9 0x9c1 25 0xbc1 10 0x9c2 26 0xbc2 11 0x9c3 27 0xbc3 12 0x9c4 28 0xbc4 13 0x9c5 29 0xbc5 14 0x9c6 30 0xbc6 15 0x9c7 31 0xbc7 bit default name description 7?0 ? actual rx group id this field contains the value of the gr oup id field from the icp cells for this facility. range: 0x00?0xff note: the value in this register is undefined when there is no valid ima cell stream present on the link. the value in this register is also undefined for a maximum of two seconds following the creation of a group containing this link.
registers 28529-dsh-001-k mindspeed technologies ? 244 mindspeed proprietary and confidential 2.7 atm cell capture registers the atm cell capture regist ers allow an atm cell to be captured fr om a facility for diagnostic purposes. 2.7.1 0xe00-0xe2f?cell_cap_payld n (capture payload contents register) these registers hold the 48 byte payload contents of a captured atm cell. these registers are read-only. 2.7.2 0xe30?cap_fac (cap ture facility register) the capture facility register configures the facility that the atm cells will be captured from. 2.7.3 0xe31?cap_cntl (capture control register) the capture control register enables the capture circuit to store an incoming atm cell as well as determine the type of atm cell stored note: when a facility is configured to be part of an ima group, a valid cell stream must be present on the input port or the values contained in these registers are undefined. the values in these registers are also undefined for a m aximum of two seconds fo llowing the creation of a group containing the specified facility in 0xe30. if the facility is configured for passthrough mode, the above restrictions do not apply. bit default name description 7-0 0 atmpld n contains one byte of the 48 byte payload contents of a captured atm cell. the first byte is stored in register 0xe00 and the remainder of the 48 bytes are stored consecutively in registers up to location 0xe2f. bit default name description 7-5 ? ? reserved 4-0 0 capfcl this field is programmed with the facility that atm cells will be captured from. bit default name description 7-2 ? ? reserved 1 0 captype this bit selects whether the next incoming icp cell is stored or simp ly the next atm cell, regardless of type, is stored. 0 = icp cell only 1 = any cell (data cell, filler cell, or icp/sicp cell) 0 0 encap enables the capture circuit to store the next in coming cell qualified by the cell type programmed in bit 1. this bit is written to a ?1? to arm th e capture circuit to store the atm cell. this bit is should be written to a ?0? once the atm cell is captured. see register 0xe32 for the capture status.
registers 28529-dsh-001-k mindspeed technologies ? 245 mindspeed proprietary and confidential 2.7.4 0xe32?cap_stat (capture status register) the capture status regist er indicates the status of the atm cell capture. bit default name description 7-1 ? reserved 0 0 cellcap this bit shows whether an atm cell has been capture d. this status bit is only valid when the capture control bit is enabled. 1 = cell has been stored 0 = cell has not been stored
28529-dsh-001-k mindspeed technologies ? 246 mindspeed proprietary and confidential 3.0 product specification 3.1 absolute maximum ratings the absolute maximum ratings in ta b l e 3-1 indicate the maximum stresses that the m2852x can tolerate without risking permanent damage. these ratings are not typical of normal operation of the device. exposure to absolute maximum rating conditions for extended periods of time may affect the device?s reliabilit y. this device should be handled as an esd-sensitive device. voltage on any signal pin that exceeds the power supply voltage by more than +0.5 v can induce destructive latchup. table 3-1. absolute maximum ratings (general) parameter value supply voltage - vdd33 ?0.5 to +3.6 v supply voltage - vdd18 ?0.5 to +1.98 v esd voltage (vgg) ?0.5 to +5.5 v input voltage ?0.5 to (vdd33 + 1.89v) storage temperature ?40 c to 125 c operating temperature range ?40 c to 85 c lead temperature +240 c for 10 seconds junction temperature +125 c static discharge voltage (human body model) 2000 v static discharge voltag e (charge device model) 350 v latch-up current 150 ma at 85 c dc input current 20 ma note: please refer to mindspeed smt application not e for the pb-free devices and for the detail explination of how jedec determines t he reflow temperatures based on package thickness: http://mindspeed.com/mspd/support/quality/smt-pb-free.pdf table 3-2. absolute maximum ratings (m28525/m28529) parameter value ja no airflow ~20 c/w
product specification 28529-dsh-001-k mindspeed technologies ? 247 mindspeed proprietary and confidential 3.2 recommended operating conditions 3.3 dc characteristics ta bl e 3-4 lists the dc characteristics of the m2852x. ta bl e 3-5 lists power characteristics of the device. table 3-4. dc characteristics table 3-3. recommended operating conditions symbol parameter minimum nominal maximum units vdd33 3.3v power supply 3.135 3.3 3.465 v vdd18 1.8v power supply 1.71 1.8 1.89 v tamb ambient operating temperature -40 25 85 c parameter minimum typical maximum comments power supply vdd33 3.0 3.3 3.6 vdc 10% power supply vdd18 1.71 1.8 1.89 vdc 5% esd voltage vgg (3.3 v or 5 v) (1,2) 3.0 3.3/5 (3) 5.5 vdc input low voltage (vil)?ttl 0 ? 0.8 vdc input high voltage (vih)?ttl 2.0 ? 5.25 vdc output voltage low (ttl) ? ? 0.4 volts; i oh = 4.0 ma output voltage high (ttl) 2.4 ? ? volts; i oh = 1500 a input leakage current ?10 ? 10 a; vin = pwr or gnd three-state output leakage current ?10 ? 10 a; vout = pwr or gnd input capacitance ? ? 7 pf output capacitance ? ? 7 pf bidirectional capacitance ? ? 7 pf footnote: (1) with 5 v logic input, vgg should be tied to 5 v. with 3.3 v lo gic input, vgg should be tied to 3.3 v. vgg must be equal or g reater than power supply voltage. (2) when vgg is operated at 5 v, se quence vgg to vdd33 as discussed in chapter 4.0 . (3) typical value for vgg is 3.3 or 5 v.
product specification 28529-dsh-001-k mindspeed technologies ? 248 mindspeed proprietary and confidential table 3-5. power characteristics (m28529) conditions parameter minimum typical maximum comments e1 utopia-serial ima_sysclk = 49.152mhz ima_refclk = 49.152mhz microclk = 25mhz 8 ima groups with 4 links each vdd33 ? 100 ? mw vdd18 ? 290 ? mw t1 utopia-serial ima_sysclk = 37.056mhz ima_refclk = 49.152mhz microclk = 25mhz 8 ima groups with 4 links each vdd33 ? 100 ? mw vdd18 ? 240 ? mw interleaved highway utopia-serial ima_sysclk = 49.152mhz ima_refclk = 49.152mhz microclk = 25mhz 8 ima groups with 4 links each vdd33 ? 100 ? mw vdd18 ? 355 ? mw e1 utopia-utopia ima_sysclk = 49.152mhz ima_refclk = 49.152mhz microclk = 25mhz 8 ima groups with 4 links each vdd33 ? 200 ? mw vdd18 ? 260 ? mw dsl 2.304mbs utopia-utopia ima_sysclk = 66mhz ima_refclk = 49.152mhz microclk = 66mhz 8 ima groups with 4 links each vdd33 ? 235 ? mw vdd18 ? 410 ? mw dsl 5.4mbs utopia-utopia ima_sysclk = 66mhz ima_refclk = 49.152mhz microclk = 66mhz 8 ima groups with 4 links each vdd33 ? 300 ? mw vdd18 ? 425 ? mw
product specification 28529-dsh-001-k mindspeed technologies ? 249 mindspeed proprietary and confidential 3.4 timing specifications this section provides timing diagrams and descriptions for the various interfaces of the m2852x. the timing relationship labels are numbered when they occur more than once in a diagram, so each label is unique. this numbering aids in identifying the appropriate label in the timing table. signals are measured at the 50% point of the changing edge, except for those involving high impe dance transitions, which are measured at 10% and 90%. figure 3-1 and figure 3-2 illustrate how input and ou tput waveforms are defined. figure 3-1. input waveform figure 3-2. output waveform t per 2.0 v 1.4 v 0.8 v t pwh 2.4 v 1.4 v 0.4 v t pwl t per
product specification 28529-dsh-001-k mindspeed technologies ? 250 mindspeed proprietary and confidential 3.4.1 reset timing figure 3-3 and ta bl e 3-6 show the timing requirements for the asynchronous reset input to the device. 3.4.2 microprocessor timing figures 3-4 through 3-7 and ta b l e s 3-7 through 3-10 show the timing requirements and characteristics of the microprocessor interface. capacitive load on all signals is 50pf. figure 3-3. reset timing table 3-6. reset timing parameters symbol parameter minimum typical maximum units t w reset minimum pulse width 100 ns figure 3-4. microprocessor timing ?asynchronous read t w reset* t dislz t enzl t dis t pd t en t h t pwl t s t pwh t h t pwl t s (high) (low) microaddr[11:0] mcs* mrd* microdata[7:0] mrdy mwr* msyncmode
product specification 28529-dsh-001-k mindspeed technologies ? 251 mindspeed proprietary and confidential table 3-7. microprocessor timing parameters - asynchronous read label description minium maximum units t per microprocessor clock (1) 15 ns t pwh pulse width high 4 * t per ?ns t pwl pulse width low 4 * t per ?ns t s setup, microaddr[11:0] to the falling edge of (mcs* + mrd*) (2) 2?ns t h hold, microaddr[11:0] from the rising edge of (mcs* + mrd*) (3) 7?ns t en enable, microdata[7:0] from the falling edge of (mcs* + mrd*) (2) 410ns t pd propagation delay, microdata[7:0] from the falling edge of (mcs* + mrd*) (2) 2 *t per 3 * t per +10 ns t dis disable, microdata[7:0] from th e rising edge of (mcs* + mrd*) (3) 410ns t enzl enable, mrdy from the falling edge of (mcs* + mrd*) (2) 410ns t dislz disable, mrdy from the falling edge of (mcs* + mrd*) (2) 3 * t per 4 * t per +10 ns footnote: (1) the microprocessor clock is required by internal logic but has no relations hip with the i/o signals. (2) timing starts from whichever is asserted last. (3) timing relative to whic hever goes inactive first. (4) timing relative to a 50pf load. figure 3-5. microprocessor timing ?asynchronous write t dislz t enzl t pwh t h2 t h1 t pwl t s1 t pwh t h2 t h1 t pwl t s2 t s1 (high) (low) microaddr[11:0] microdata[7:0] msyncmode mcs* mwr* mrdy mrd*
product specification 28529-dsh-001-k mindspeed technologies ? 252 mindspeed proprietary and confidential table 3-8. microprocessor timing parameters - asynchronous write label description minimum maximum units t per microprocessor clock (1) 15 ns t pwl pulse width low (mcs* + mwr*) 4 * t per ?ns t pwh pulse width high (mcs* + mwr*) 4 * t per ?ns t s1 setup, microaddr[11:0] to the falling edge of (mcs* + mwr*) (2) 2?ns t h1 hold, microaddr[11:0] from the rising edge of (mcs* + mwr*) (3) 7?ns t s2 setup, microdata[7:0] from the falling edge of (mcs* + mwr*) (2) ?t per ns t h2 hold, microdata[6:0] from the rising edge of (mcs* + mwr*) (3) 7?ns t enzl enable, mrdy from the falling edge of (mcs* + mwr*) (2) 410ns t dislz disable, mrdy from the falling edge of (mcs* + mwr*) (2) 3 * t per 4 * t per +10 ns footnote: (1) the microprocessor clock is required by internal logic but has no relations hip with the i/o signals. (2) timing starts from whichever is asserted last. (3) timing relative to whic hever goes inactive first. (4) timing relative to a 50pf load. figure 3-6. microprocessor timing ?synchronous read t dislz t enzl t dis t pd t en t h t s t h t s t h t s t h t s t per (high) microclk mcs* mwr* mas* m icroaddr[11:0] microdata mrdy microint* msyncmode
product specification 28529-dsh-001-k mindspeed technologies ? 253 mindspeed proprietary and confidential table 3-9. microprocessor timing parameters - synchronous read label description minimum maximum units t per microprocessor clock period 40 ns t duty microprocessor clock period duty cycle 40 60 % t s setup to the rising edge of microclk 5 ? ns t h hold from the rising edge of microclk 2 ? ns t en enable from the rising edge of microclk 2 15 ns t pd propagation delay from the rising edge of microclk 2 26 ns t dis propagation delay from the falling edge of microclk 2 15 ns t enzl enable from the rising edge of microclk 2 15 ns t dislz disable from the rising edge of microclk 2 15 ns footnote: (1) timing relative to a 50pf load figure 3-7. microprocessor timing ?synchronous write t enzl t h t s t h t s t h t s t h t s t h t s t per (high) microclk mcs* mw r* mas* microaddr[11:0] microdata[7:0] mrdy microint* msyncmode
product specification 28529-dsh-001-k mindspeed technologies ? 254 mindspeed proprietary and confidential 3.4.3 phy-side interface timing (serial mode) the phy-side interface on the maxima supports three different modes of operation, serial, interleaved and utopia. figure 3-8 through 3-13 show the timing diagrams for t1/e1/dsl mode. ta b l e 3-11 and ta bl e 3-12 show the phy-side timing requirements for t1/e1/dsl mode. table 3-10. microprocessor timing parameters - synchronous write label description minimum maximum units t per microprocessor clock period 40 ns t duty microprocessor clock period duty cycle 40 60 % t s setup to the rising edge of microclk 5 ? ns t h hold from the rising edge of microclk 2 ? ns t enzl enable from the rising edge of microclk 2 15 ns footnote: (1) timing relative to a 50pf load figure 3-8. phy-side serial t1/e1/dsl mode transmit timing (txclkpol = 0, txdatshft = 0) figure 3-9. phy-side serial t1/e1/dsl mode transmit timing (txclkpol = 1, txdatshft = 0) t pd t h t h t s t s sptxclk sptxsync (input) sptxdata t pwh t pwl t per sptxsync (o utput) t pd t pd t pd t h t h t s t s sptxclk sptxsync (input) sptxdata t pwh t pwl t per sptxsync (o utput) t pd t pd
product specification 28529-dsh-001-k mindspeed technologies ? 255 mindspeed proprietary and confidential figure 3-10. phy-side serial t1/e1/dsl mode transmit timing (txclkpol = 0, txdatshft = 1) figure 3-11. phy-side serial t1/e1/dsl mode transmit timing (txclkpol = 1, txdatshft = 1) table 3-11. phy-side serial t1/e1/dsl mode transmit timing parameters symbol parameter minimum typical maximum units t per serial transmit clock period 50 ns t pwh serial clock pulse width (high) 20 ns t pwl serial clock pulse width (low) 20 ns t s setup to sptxclk rise(fall) (1) edge 5 ns t h hold from sptxclk rise(fall) (1) edge 3 ns t pd delay from sptxclk rise(fall) (1) edge 1 20 ns footnote: (1) timing synchronized to fall ing edge when txclkpol = 1 general note: 1. the txclkpol (bit 3) in the iomode regi ster determines whether timing is referenced to the positi ve or negative clock edge. 2. all outputs are assumed to have 20 pf loading. t pd t h t h t s t s sptxclk sptxsync (input) sptxdata t pwh t pwl t per sptxsync (o utput) t t pd pd t pd t h t h t s t s sptxclk sptxsync (input) sptxdata t pwh t pwl t per sptxsync (output) t t pd pd
product specification 28529-dsh-001-k mindspeed technologies ? 256 mindspeed proprietary and confidential figure 3-12. phy-side serial t1/e1/dsl mode receive timing (positive clock edge timing- rxclkpol = 0) figure 3-13. phy-side serial t1/e1/dsl mode receive timing (negative clock edge timing- rxclkpol = 1) table 3-12. phy-side serial t1/e1/dsl mode receive timing parameters symbol parameter minimum typical maximum units t per serial receive clock period 50 ns t pwh serial receive clock pulse width (high) 20 ns t pwl serial receive clock pulse width (low) 20 ns t s1 setup to sprxclk rise(fall) (1) edge 5 ns t h1 hold from sprxclk rise(fall) (1) edge 3 ns t s2 setup to sprxclk rise(fall) (1) edge 5 ns t h2 hold from sprxclk rise(fall) (1) edge 3 ns footnote: (1) timing synchronized to falling clock edge when rxclkpol = 1 general note: 1. the rxclkpol (bit 5) in the iomode regi ster determines whether timing is synchroniz ed to the positive or negative clock edge. 2. all outputs are assumed to have 20 pf loading. t h2 t h2 t s2 t s2 t h1 t s1 sprxclk sprxdata sprxsync t pwh t pwl t per t h2 t h2 t s2 t s2 t h1 t s1 t pwl sprxclk sprxdata srpxsync t pwh t per
product specification 28529-dsh-001-k mindspeed technologies ? 257 mindspeed proprietary and confidential 3.4.4 fractional t1/e1 mode timing figure 3-14 and show the phy-side interface timing when configured for fractional t1/e1 mode. ta bl e 3-13 and 3- 14 show the phy-side timing requirements for fractional t1/e1 mode. figure 3-14. fractional t1/e1 transmit timing table 3-13. fractional t1/e1 transmit timing parameters symbol parameter minimum typical maximum units t per fractional transmit clock period 50 ns t pwh fractional transmit clock pulse width (high) 20 ns t pwl fractional transmit clo ck pulse width (low) 20 ns t s set up time to sptxclk rising edge 5 ns t h hold time from sptxclk falling edge 5 ns t pd delay from sptxclk rising edge 1 20 ns t per sptxclk sptxdata t pd t pd sptxsync t s t h t pwl t pwh
product specification 28529-dsh-001-k mindspeed technologies ? 258 mindspeed proprietary and confidential figure 3-15. fractional t1/e1 receive timing table 3-14. fractional t1/e1 receive timing parameters symbol parameter minimum typical maximum units t per serial receive clock period 50 ns t pwh serial receive clock pulse width (high) 20 ns t pwl serial receive clock pulse width (low) 20 ns t s1 setup to sprxclk rising edge 5 ns t h1 hold from sprxclk falling edge 5 ns t s2 setup to sprxclk rising edge 10 ns t h2 hold from sprxclk rising edge 10 ns t per t s1 t h1 sprxclk sprxsync sprxdata s2 t t h2 pwh pwl t t
product specification 28529-dsh-001-k mindspeed technologies ? 259 mindspeed proprietary and confidential 3.4.5 phy-side interface mode (interleaved highway) figure 3-16 and 3-21 show the phy-side interface timing when configured for interleaved highway mode. ta bl e 3- 15 and 3-16 show the phy-side timing requirements for interleaved highway mode. figure 3-16. phy-side interleaved highway mode transmit timing (ihtxclkpolx = 0, ihtxdatshftx = 0)) figure 3-17. phy-side interleaved highway mode transmit timing (ihtxclkpolx = 1, ihtxdatshftx = 0) t pd t h t h t s t s t h t h t s t s t per ihtxclk ihtxsync ihtxindo ihtxdata t pwh t pwl t pd t h t h t s t s t h t h t s t s t per ihtxclk ihtxsync ihtxindo ihtxdata t pwl t pwh
product specification 28529-dsh-001-k mindspeed technologies ? 260 mindspeed proprietary and confidential figure 3-18. phy-side interleaved highway mode transmit timing (ihtxclkpolx = 0, ihtxdatshftx = 1) figure 3-19. phy-side interleaved highway mode transmit timing (ihtxclkpolx = 1, ihtxdatshftx = 1) table 3-15. phy-side interleaved highway mode transmit timing parameters symbol parameter minimum typical maximum units t per ih transmit clock period 50 ns t pwh ih transmit clock pulse width (high) 20 ns t pwl ih transmit clock pulse width (low) 20 ns t s setup to ihtxclk rise(fall) (1) edge 5 ns t h hold from ihtxclk rise(fall) (1) edge 3 ns t pd delay from ihtxclk rise(fall) (1) edge 2 20 ns footnote: (1) timing synchronized to falling clock edge when ihtxclkpolx = 1 general note: 1. all outputs are assumed to have 20 pf loading. t pd t h t h t s t s t h t h t s t s t per ih txc lk ih txs ync ih txind o ih txd ata t pwh t pwl t pd t h t h t s t s t h t h t s t s t per ih t xc lk ih t xs ync ih t xind o ih t xd ata t pwl t pwh
product specification 28529-dsh-001-k mindspeed technologies ? 261 mindspeed proprietary and confidential figure 3-20. phy-side interleaved highway mode receive timing (positive edge - ihrxclkpolx = 0) figure 3-21. phy-side interleaved highway mode receive timing (negative edge - ihrxclkpolx = 1) table 3-16. phy-side interleaved highway mode receive timing parameters symbol parameter minimum typical maximum units t per ih receive clock period 50 ns t pwh ih receive clock pul se width (high) 20 ns t pwl ih receive clock pul se width (low) 20 ns t s setup to ihrxclk rise(fall) (1) edge 5 ns t h hold from ihrxclk rise(fall) (1) edge 3 ns footnote: (1) timing synchronized with falli ng clock edge when rxclkpolx = 1 general note: 1. all outputs are assumed to have 20 pf loading. t h t s t h t h t s t s t h t h t s t s t per ihr xclk ih r xsync ihr xindo ihr xdata t pwh t pwl t h t s t h t h t s t s t h t h t s t s t per ih r xc lk ih r xs ync ih r xind o ih r xd ata t pwl t pwh
product specification 28529-dsh-001-k mindspeed technologies ? 262 mindspeed proprietary and confidential 3.4.6 phy-side interface timing (utopia) figures 3-22 through 3-23 and ta bl e s 3-17 through 3-18 show the timing requirements and characteristics of the phy-side utopia interface. figure 3-22. phy-side utopia transmit timing table 3-17. phy-side utopia transmit timing parameters symbol parameter minimum typical maximum units t per (1) utopia transmit clock period 30.3 ns t duty utopia transmit clock dutycycle 50 % t s setup to phyutxclk rise edge 8 ns t h hold from phyutxclk rise edge 1 ns t pd enable from phyutxclk fall edge -5 7 ns footnote: (1) this clock is a divi de-by-2 of ima_sysclk. general note: 1. timing applies with 0-50pf loads on the outputs. t pd t pd t pd t pd t pd t h t s t per phyutxclk phyutxenb* phyutxaddr[4:0] phyutxdata[15:0] phyutxsoc phyutxprty phyutxclav
product specification 28529-dsh-001-k mindspeed technologies ? 263 mindspeed proprietary and confidential figure 3-23. phy-side utopia receive timing table 3-18. phy-side utopia receive timing parameters symbol parameter minimum typical maximum units t per (1) utopia receive clock period 30.3 ns t duty utopia receive clock dutycycle 50 % t s setup to phyurxclk rise edge 8 ns t h hold from phyurxclk rise edge 1 ns t pd enable from phyurxclk fall edge -5 7 ns footnote: (1) this clock is a divi de-by-2 of ima_sysclk. general note: 1. timing applies with 0-50pf loads on the outputs. t pd t pd t h t s t per phyurxclk phyurxenb* phyurxaddr[4:0] phyurxdata[15:0] phyurxsoc phyurxprty phyurxclav t h t s t h t s t h t s
product specification 28529-dsh-001-k mindspeed technologies ? 264 mindspeed proprietary and confidential 3.4.7 utopia interface timing (atm-side) figures 3-24 through 3-25 and ta bl e s 3-19 through 3-22 show the timing requirements and characteristics of the atm-side utopia interface. figure 3-24. atm-side utopia transmit timing table 3-19. atm-side utopia transmit timing parameters (ima enabled - 16 bit mode) symbol parameter minimum typical maximum units t per utopia transmit clock period 20 (1) ns t duty utopia transmit clock dutycycle 40 60 % t s setup to atmutxclk rise edge 4 ns t h hold from atmutxclk rise edge 1 ns t pd delay from atmutxclk rise edge 1 15 ns t en enable from atmutxclk rise edge 1 15 ns t dis disable from atmutxclk rise edge 1 15 ns general note: 1. timing applies with 0-30pf loads on the outputs. t dis t pd t en t h t s t h t s t h t s t h t s t per atmutxclk atmutxenb* atmutxaddr[4:0] atmutxdata[15:0] atmutxsoc atmutxprty atmutxclav
product specification 28529-dsh-001-k mindspeed technologies ? 265 mindspeed proprietary and confidential table 3-20. atm-side utopia transmit timing parameters (ima bypassed - 8/16 bit mode, ima enabled - 8 bit mode) symbol parameter minimum typical maximum units t per utopia transmit clock period 30.3 ns t duty utopia transmit clock dutycycle 40 60 % t s setup to atmutxclk rise edge 8 ns t h hold from atmutxclk rise edge 1 ns t pd delay from atmutxclk rise edge 1 20 ns t en enable from atmutxclk rise edge 1 20 ns t dis disable from atmutxclk rise edge 1 20 ns general note: timing applies with 0-30pf loads on the outputs. figure 3-25. atm-side utopia receive timing t dis t pd t en t dis t pd t en t dis t pd t en t dis t pd t en t h t s t h t s t per atmurxclk atmurxenb* atmurxaddr[4:0] atmurxdata[15:0] atmurxprty atmurxsoc atmurxclav
product specification 28529-dsh-001-k mindspeed technologies ? 266 mindspeed proprietary and confidential table 3-21. atm-side utopia receive timing parameters (ima enabled - 16 bit mode) symbol parameter minimum typical maximum units t per utopia receive clock period 20 (1) ns t duty utopia receive clock dutycycle 40 60 % t s setup to atmurxclk rise edge 4 ns t h hold from atmurxclk rise edge 1 ns t pd delay from atmurxclk rise edge 1 15 ns t en enable from atmurxclk rise edge 1 15 ns t dis disable from atmurxclk rise edge 1 15 ns general note: 1. timing applies with 0-30 pf loads on the outputs. table 3-22. atm-side utopia receive timing parameters (ima bypassed - 8/16 bit mode, ima enabled - 8 bit mode) symbol parameter minimum typical maximum units t per utopia receive clock period 30.3 ns t duty utopia receive clock dutycycle 40 60 % t s setup to atmurxclk rise edge 8 ns t h hold from atmurxclk rise edge 1 ns t pd delay from atmurxclk rise edge 1 20 ns t en enable from atmurxclk rise edge 1 20 ns t dis disable from atmurxclk rise edge 1 20 ns general note: 1. timing applies with 0-30 pf loads on the outputs.
product specification 28529-dsh-001-k mindspeed technologies ? 267 mindspeed proprietary and confidential 3.4.8 external memory interface timing diagram figure 3-26. external memory timing write data read data t wdh t wdpd t opd t opd t wpd t wpd t cpd t cpd t cpd t cpd t adpd t adpd t adpd t adpd t apd t apd t apd t rdh t rds read cycle read cycle write cycle t per write cycle memctrl_clk memaddr memctrl_adsc* memctrl_ce* memctrl_we* memctrl_oe* memdata
product specification 28529-dsh-001-k mindspeed technologies ? 268 mindspeed proprietary and confidential 3.4.9 jtag interface timing figure 3-27 and ta b l e 3-24 show the timing requirements and characteristics of the jtag interface. table 3-23. external memory timing parameters symbol parameter minimum typical maximum units t pwl pulse width low 8 - ns t pwh pulse width high 8 - ns t per period 20 - ns t apd propagation delay, memaddr from rising edge of memctrl_clk 110ns t adpd propagation delay, memctrl_adsc from rising edge of memctrl_clk 110ns t cpd propagation delay, memctrl_ce* from rising edge of memctrl_clk 110ns t wpd propagation delay, memctrl_we* from rising edge of memctrl_clk 110ns t opd propagation delay, memctrl_oe* from rising edge of memctrl_clk 110ns t wdpd propagation delay, valid write data from rising edge of memctrl_clk -10ns t wdh hold, valid write data from rising edge of memctrl_clk 1 - ns t rds setup, read data to rising edge of memctrl_clk 5 - ns t rdh hold, read data from rising edge of memctrl_clk 1 - ns footnote: (1) all outputs are assumed to have a load of 20pf figure 3-27. jtag timing t dis2 t dis1 t pd t en t h t s t h t s t rec t per tck trst* tms tdi tdo
product specification 28529-dsh-001-k mindspeed technologies ? 269 mindspeed proprietary and confidential 3.4.10 one-second interface timing figure 3-28 and ta b l e 3-25 show the timing requirements and characteristics of the one-second interface. table 3-24. jtag timing parameters symbol parameter minimum typical maximum units t per tck clock period 100 ns t duty tck clock duty cycle 40 60 % t rec recovery, tck rise edge from trst_n rise edge 10 ns t s setup to tck rise edge 10 ns t h hold from tck rise edge 10 ns t pd delay from tck fall edge 15 ns t en enable from tck fall edge 15 ns t dis1 disable from tck fall edge 15 ns t dis2 disable from tck fall edge 15 ns footnote: (1) all outputs are assumed to have a load of 80pf figure 3-28. one-second timing table 3-25. one second timing parameters label description min max unit 8khzin clock frequency 0.01 100 khz t per 8khzin duty cycle 40% 60% t pd propagation delay, onesecout from the rising edge of onesecclk 1 20 ns general notes: t pd t pd t per t pwl1 t pwh1 8khzin onesecio 500027_033 when onesecio is configured as an output, it is equal to 8khzin/8000.
product specification 28529-dsh-001-k mindspeed technologies ? 270 mindspeed proprietary and confidential 3.5 package specification 3.5.1 mechanical description the m28525/9 is a 484-ball, 27mm pbga package. a mechanical drawing of the device is provided in figure 3-29 and figure 3-30 . figure 3-29. m28525/9 mechanical drawing (bottom view)
product specification 28529-dsh-001-k mindspeed technologies ? 271 mindspeed proprietary and confidential figure 3-30. m28525/9 mechanical drawing (top and side views)
product specification 28529-dsh-001-k mindspeed technologies ? 272 mindspeed proprietary and confidential 3.6 interface pin description figure 3-31. m28529 pinout diagram, utopia-to-serial (bottom view) 2625242322212019181716151413121110987654321 a atmurxd ata[15] nc atmurxd ata[7] atmurxd ata[6] atmurxd ata[2] atmurxcl av[1] atmurxen b[0]* txtrl[0] sprxclk[2 ] sprxsync [1] sprxdata [1] sptxclk[0 ] sptxsync [0] sptxsync [1] sptxdata[ 1] sprxclk[4 ] sprxclk[7 ] sprxsync [7] sprxdata [6] sptxclk[6 ] sptxsync [6] sptxdata[ 6] sptxdata[ 7] sprxsync [10] tck vss a b atmurxad dr[3] atmurxd ata[14] atmurxd ata[11] atmurxd ata[10] atmurxd ata[5] atmurxd ata[1] atmurxcl av[0] txtrl[1] sprxclk[0 ] sprxsync [0] sprxsync [3] sprxdata [3] sptxclk[3 ] sptxsync [2] vss sprxclk[6 ] sprxsync [5] sprxdata [5] sptxclk[5 ] sptxsync [5] sptxdata[ 5] sprxclk[8 ] sprxsync [8] sprxclk[1 1] vss nc b c atmutxen b[1]* atmurxad dr[2] vdd33 atmurxd ata[12]' atmurxd ata[9] atmurxd ata[4] atmurxd ata[0] atmurxs oc vdd33 sprxclk[1 ] sprxsync [2] sprxdata [2] sptxclk[2 ] sptxsync [3] sptxdata[ 3] sprxsync [4] sprxdata [4] sptxclk[4 ] sptxsync [4] sptxsync [7] sprxclk[1 0] trst* tdi tdo sprxdata [8] sprxdata [10] c d atmutxprt y atmutxen b[0]* atmurxad dr[1] vss atmurxd ata[13] atmurxd ata[8] atmurxd ata[3] atmurxpr ty atmurxen b[1]* vss sprxclk[3 ] sprxdata [0] sptxclk[1 ] sptxdata[ 0] sprxclk[5 ] sprxsync [6] sprxdata [7] sptxclk[7 ] sptxdata[ 4] sprxclk[9 ] sprxsync [9] tms vgg sprxsync [11] sprxdata [11] sptxclk[1 0] d e atmutxda ta[0] atmutxcl av[1] atmurxad dr[4] atmurxad dr[0] vss vss vdd33 vdd33 ima_sysc lk vdd18 ima_refcl k vdd33 vss sptxdata[ 2] vdd33 vdd33 vdd18 vdd18 vdd33 vdd33 vss vss sprxdata [9] sptxclk[9 ] sptxclk[1 1] sptxsync [10] e f atmutxda ta[4] atmutxda ta[1] atmutxs oc atmurxcl k vss vss sptxclk[8 ] sptxsync [9] sptxsync [11] sptxdata[ 10] f g atmutxda ta[8] atmutxda ta[5] atmutxda ta[3] atmutxcl av[0] vdd33 vdd33 sptxsync [8] sptxdata[ 9] sptxdata[ 11] sprxclk[1 2] g h atmutxda ta[12] atmutxda ta[9] atmutxda ta[6] atmutxda ta[2] vdd33 vdd33 sptxdata[ 8] sprxclk[1 4] sprxclk[1 5] sprxsync [12] h j atmutxda ta[15] atmutxda ta[13] atmutxda ta[10] atmutxda ta[7] vdd18 vdd18 sprxclk[1 3] sprxsync [14] sprxsync [15] sprxdata [12] j k atmutxad dr[3] atmutxad dr[1] atmutxda ta[14] atmutxda ta[11] vdd18 vdd18 vdd18 vdd33 vss vss vdd33 vdd18 vdd18 vdd18 sprxsync [13] sprxdata [13] sprxdata [15] sptxclk[1 2] k l memctrl_ adsc* atmutxad dr[4] atmutxad dr[2] atmutxad dr[0] vdd33 vdd18 vss vss vss vss vss vss vdd18 vdd33 sprxdata [14] sptxclk[1 3] sptxclk[1 4] sptxsync [12] l m memdata[ 0] memctrl_ oe* memctrl_ we* atmutxcl k vdd33 vdd33 vss vss vss vss vss vss vdd33 vdd33 sptxclk[1 5] sptxsync [13] vdd33 sptxsync [15] m n memdata[ 3] memdata[ 2] memdata[ 1] memctrl_ ce* vss vss vss vss vss vss vss vss vss sptxsync [14] sptxdata[ 12] sptxdata[ 13] vss sptxdata[ 14] n p memdata[ 4] memdata[ 5] memdata[ 6] memdata[ 7] memdata[ 9] vss vss vss vss vss vss vss vss vss microaddr[ 8] microaddr[ 10] microaddr[ 11] sptxdata[ 15] p r memdata[ 8] vss memdata[ 10] memdata[ 12] vdd33 vdd33 vss vss vss vss vss vss vdd33 microclk microaddr[ 4] microaddr[ 6] microaddr[ 7] microaddr[ 9] r t memdata[ 11] memdata[ 13] memdata[ 14] memaddr[ 1] vdd33 vdd18 vss vss vss vss vss vss vdd18 vdd33 reset* microaddr[ 1] microaddr[ 3] microaddr[ 5] t u memdata[ 15] memaddr[ 0] memaddr[ 3] memaddr[ 6] vdd18 vdd18 vdd18 vdd33 vss vss vdd33 vdd18 vdd18 vdd18 microdata[ 5] vdd33 microaddr[ 0] microaddr[ 2] u v memaddr[ 2] memaddr[ 4] memaddr[ 7] memaddr[ 10] vdd18 vdd18 microdata[ 1] microdata[ 4] microdata[ 7] mcs* v w memaddr[ 5] memaddr[ 8] memaddr[ 11] memaddr[ 14] vdd33 vdd33 mrd* microdata[ 0] microdata[ 3] microdata[ 6] w y memaddr[ 9] memaddr[ 12] memaddr[ 15] memaddr[ 17] vdd33 vdd33 sprxsync [16] mrdy mwr* microdata[ 2] y a a memaddr[ 13] memaddr[ 16] memaddr[ 19] nc vss vss sprxdata [16] sprxsync [17] sprxclk[1 6] microint* aa a b memaddr[ 18] memctrl_ clk statout[0] nc vss vss vdd33 vdd33 vdd18 vdd18 vdd33 vdd33 sptxclk[2 7] vss vdd33 vdd33 vdd18 vdd18 vdd33 vdd33 vss vss sptxclk[1 7] sprxdata [17] sprxclk[1 9] sprxclk[1 7] ab a c extmems el nc vss vgg testenabl e[1] sptxdata[ 29] sptxsync [29] sptxclk[2 8] sprxdata [28] sptxdata[ 27] sptxsync [27] sptxclk[2 6] sprxdata [26] sprxsync [25] sprxclk[2 4] sptxsync [23] sptxclk[2 2] sprxdata [22] sprxsync [22] sprxclk[2 2] sptxdata[ 17] nc sptxsync [16] sptxclk[1 6] sprxsync [19] sprxclk[1 8] ac a d statout[1] 8khzin phyintfcs el scanenabl e sptxdata[ 30] sptxsync [30] sprxdata [31] sprxsync [31] sprxsync [28] sprxclk[2 8] sptxdata[ 24] sptxsync [24] sprxdata [27] sprxsync [26] sprxclk[2 6] sptxdata[ 22] sptxsync [21] sptxclk[2 1] sprxdata [21] sprxsync [21] sprxclk[2 1] sptxdata[ 16] sptxsync [17] vss sprxdata [19] sprxsync [18] ad ae onesecio tristate msyncmo de sptxdata[ 28] sptxsync [28] sptxclk[2 9] sprxdata [29] sprxsync [29] sprxclk[2 9] sptxdata[ 25] sptxsync [26] vss sptxclk[2 5] sprxsync [27] sprxclk[2 7] sptxdata[ 23] sptxdata[ 20] sptxsync [20] sptxclk[2 0] sprxdata [20] sprxsync [20] sprxclk[2 0] sptxdata[ 18] vdd33 sptxclk[1 9] sprxdata [18] ae af testenabl e[0] sptxdata[ 31] sptxsync [31] sptxclk[3 1] sptxclk[3 0] sprxdata [30] sprxsync [30] sprxclk[3 1] sprxclk[3 0] sptxdata[ 26] sptxsync [25] sptxclk[2 4] sprxdata [25] sprxdata [24] sprxsync [24] sprxclk[2 5] sptxdata[ 21] sptxsync [22] sptxclk[2 3] sprxdata [23] sprxsync [23] sprxclk[2 3] sptxdata[ 19] sptxsync [19] sptxsync [18] sptxclk[1 8] af 2625242322212019181716151413121110987654321 jtag serial tx utopia rx serial rx utopia tx external memory microprocessor bottom view
product specification 28529-dsh-001-k mindspeed technologies ? 273 mindspeed proprietary and confidential figure 3-32. m28525 pinout diagram utopia-to-serial (bottom view) 2625242322212019181716151413121110987654321 a atmurxd ata[15] nc atmurxd ata[7] atmurxd ata[6] atmurxd ata[2] atmurxcl av[1] atmurxe nb[0]* txtrl[0] sprxclk[ 2] sprxsync [1] sprxdata [1] sptxclk[0 ] sptxsync [0] sptxsync [1] sptxdata [1] sprxclk[ 4] sprxclk[ 7] sprxsync [7] sprxdata [6] sptxclk[6 ] sptxsync [6] sptxdata [6] sptxdata [7] sprxsync [10] tck vss a b atmurxa ddr[3] atmurxd ata[14] atmurxd ata[11] atmurxd ata[10] atmurxd ata[5] atmurxd ata[1] atmurxcl av[0] txtrl[1] sprxclk[ 0] sprxsync [0] sprxsync [3] sprxdata [3] sptxclk[3 ] sptxsync [2] vss sprxclk[ 6] sprxsync [5] sprxdata [5] sptxclk[5 ] sptxsync [5] sptxdata [5] sprxclk[ 8] sprxsync [8] sprxclk[ 11] vss nc b c atmutxen b[1]* atmurxa ddr[2] vdd33 atmurxd ata[12] atmurxd ata[9] atmurxd ata[4] atmurxd ata[0] atmurxs oc vdd33 sprxclk[ 1] sprxsync [2] sprxdata [2] sptxclk[2 ] sptxsync [3] sptxdata [3] sprxsync [4] sprxdata [4] sptxclk[4 ] sptxsync [4] sptxsync [7] sprxclk[ 10] trst* tdi tdo sprxdata [8] sprxdata [10] c d atmutxpr ty atmutxen b[0]* atmurxa ddr[1] vss atmurxd ata[13] atmurxd ata[8] atmurxd ata[3] atmurxpr ty atmurxe nb[1]* vss sprxclk[ 3] sprxdata [0] sptxclk[1 ] sptxdata [0] sprxclk[ 5] sprxsync [6] sprxdata [7] sptxclk[7 ] sptxdata [4] sprxclk[ 9] sprxsync [9] tms vgg sprxsync [11] sprxdata [11] sptxclk[1 0] d e atmutxd ata[0] atmutxcl av[1] atmurxa ddr[4] atmurxa ddr[0] vss vss vdd33 vdd33 ima_sysc lk vdd18 ima_refc lk vdd33 vss sptxdata [2] vdd33 vdd33 vdd18 vdd18 vdd33 vdd33 vss vss sprxdata [9] sptxclk[9 ] sptxclk[1 1] sptxsync [10] e f atmutxd ata[4] atmutxd ata[1] atmutxs oc atmurxcl k vss vss sptxclk[8 ] sptxsync [9] sptxsync [11] sptxdata [10] f g atmutxd ata[8] atmutxd ata[5] atmutxd ata[3] atmutxcl av[0] vdd33 vdd33 sptxsync [8] sptxdata [9] sptxdata [11] sprxclk[ 12] g h atmutxd ata[12] atmutxd ata[9] atmutxd ata[6] atmutxd ata[2] vdd33 vdd33 sptxdata [8] sprxclk[ 14] sprxclk[ 15] sprxsync [12] h j atmutxd ata[15] atmutxd ata[13] atmutxd ata[10] atmutxd ata[7] vdd18 vdd18 sprxclk[ 13] sprxsync [14] sprxsync [15] sprxdata [12] j k atmutxad dr[3] atmutxad dr[1] atmutxd ata[14] atmutxd ata[11] vdd18 vdd18 vdd18 vdd33 vss vss vdd33 vdd18 vdd18 vdd18 sprxsync [13] sprxdata [13] sprxdata [15] sptxclk[1 2] k l memctrl_ adsc* atmutxad dr[4] atmutxad dr[2] atmutxad dr[0] vdd33 vdd18 vss vss vss vss vss vss vdd18 vdd33 sprxdata [14] sptxclk[1 3] sptxclk[1 4] sptxsync [12] l m memdata[ 0] memctrl_ oe* memctrl_ we* atmutxcl k vdd33 vdd33 vss vss vss vss vss vss vdd33 vdd33 sptxclk[1 5] sptxsync [13] vdd33 sptxsync [15] m n memdata[ 3] memdata[ 2] memdata[ 1] memctrl_ ce* vss vss vss vss vss vss vss vss vss sptxsync [14] sptxdata [12] sptxdata [13] vss sptxdata [14] n p memdata[ 4] memdata[ 5] memdata[ 6] memdata[ 7] memdata[ 9] vss vss vss vss vss vss vss vss vss microaddr [8] microaddr [10] microaddr [11] sptxdata [15] p r memdata[ 8] vss memdata[ 10] memdata[ 12] vdd33 vdd33 vss vss vss vss vss vss vdd33 microclk microaddr [4] microaddr [6] microaddr [7] microaddr [9] r t memdata[ 11] memdata[ 13] memdata[ 14] memaddr[ 1] vdd33 vdd18 vss vss vss vss vss vss vdd18 vdd33 reset* microaddr [1] microaddr [3] microaddr [5] t u memdata[ 15] memaddr[ 0] memaddr[ 3] memaddr[ 6] vdd18 vdd18 vdd18 vdd33 vss vss vdd33 vdd18 vdd18 vdd18 microdata [5] vdd33 microaddr [0] microaddr [2] u v memaddr[ 2] memaddr[ 4] memaddr[ 7] memaddr[ 10] vdd18 vdd18 microdata [1] microdata [4] microdata [7] mcs* v w memaddr[ 5] memaddr[ 8] memaddr[ 11] memaddr[ 14] vdd33 vdd33 mrd* microdata [0] microdata [3] microdata [6] w y memaddr[ 9] memaddr[ 12] memaddr[ 15] memaddr[ 17] vdd33 vdd33 ui/pd mrdy mwr* microdata [2] y aa memaddr[ 13] memaddr[ 16] memaddr[ 19] nc vss vss ui/pd ui/pd ui/pd microint* aa ab memaddr[ 18] memctrl_ clk statout[0] nc vss vss vdd33 vdd33 vdd18 vdd18 vdd33 vdd33 ui/pd vss vdd33 vdd33 vdd18 vdd18 vdd33 vdd33 vss vss ui/pd ui/pd ui/pd ui/pd ab ac extmems el nc vss vgg testenabl e[1] uo uio/pd ui/pd ui/pd uo uio/pd ui/pd ui/pd ui/pd ui/pd uio /pd ui/pd ui/pd ui/pd ui/pd uo nc uio/pd ui/pd ui/pd ui/pd ac ad statout[1] 8khzin phyintfcs el scanenab le uo uio/pd ui/pd ui/pd ui/pd ui/pd uo uio/pd ui/pd ui/pd ui/pd u o uio/pd ui/pd ui/pd ui/pd ui/pd uo uio/pd vss ui/pd ui/pd ad ae onesecio tristate msyncmo de uo uio/pd ui/pd ui/pd ui/pd ui/pd uo uio/pd vss ui/pd ui/pd u i/pd uo uo uio/pd ui/pd ui/pd ui/pd ui/pd uo vdd33 ui/pd ui/pd ae af testenabl e[0] uo uio/pd ui/pd ui/pd ui/pd ui/pd ui/pd ui/pd uo u io/pd ui/pd ui/pd ui/pd ui/pd ui/pd uo uio/pd u i/pd ui/pd ui/pd ui/pd uo uio/pd uio/pd ui/pd af 2625242322212019181716151413121110987654321 jtag serial tx unused output (output in tristate) (in phy-side utopia mode) utopia rx serial rx unused input intenally pulled down (in phy-side serial mode) utopia tx unused i/o (internally pulled down when in input mode, output tristate) (in phy-side serial mode) external memory microprocessor
product specification 28529-dsh-001-k mindspeed technologies ? 274 mindspeed proprietary and confidential figure 3-33. m28525/9 pinout diagram utopia-to-utopia (bottom view) 2625242322212019181716151413121110987654321 a atmurxd ata[15] nc atmurxd ata[7] atmurxd ata[6] atmurxd ata[2] atmurxcl av[1] atmurxe nb[0]* txtrl[0] ui/pd ui/pd ui/pd ui/pd uio/pd uio/pd uo ui/pd ui/pd ui/pd ui/pd ui/pd uio/pd uo uo ui/pd tck vss a b atmurxa ddr[3] atmurxd ata[14] atmurxd ata[11] atmurxd ata[10] atmurxd ata[5] atmurxd ata[1] atmurxcl av[0] txtrl[1] ui/pd ui/pd ui/pd ui/pd ui/pd uio/pd vss ui/pd ui/pd ui/pd ui/pd uio/pd uo ui/pd ui/pd ui/pd vss nc b c atmutxen b[1]* atmurxa ddr[2] vdd33 atmurxd ata[12] atmurxd ata[9] atmurxd ata[4] atmurxd ata[0] atmurxs oc vdd33 ui/pd ui/pd ui/pd ui/pd uio/pd uo ui/pd ui/pd ui/pd uio/pd uio/pd ui/pd trst* tdi tdo ui/pd ui/pd c d atmutxpr ty atmutxen b[0]* atmurxa ddr[1] vss atmurxd ata[13] atmurxd ata[8] atmurxd ata[3] atmurxpr ty atmurxe nb[1]* vss ui/pd ui/pd ui/pd uo ui/pd ui/pd ui/pd ui/pd uo ui/pd ui/pd tms vgg ui/pd ui/pd phyutxcl av[1] d e atmutxd ata[0] atmutxcl av[1] atmurxa ddr[4] atmurxa ddr[0] vss vss vdd33 vdd33 ima_sysc lk vdd18 ima_refc lk vdd33 vss uo vdd33 vdd33 vdd18 vdd18 vdd33 vdd33 vss vss ui/pd ui/pd phyutxcl av[0] phyutxen b[0]* e f atmutxd ata[4] atmutxd ata[1] atmutxs oc atmurxcl k vss vss ui/pd phyutxen b[1]* phyutxad dr[4] phyutxad dr[1] f g atmutxd ata[8] atmutxd ata[5] atmutxd ata[3] atmutxcl av[0] vdd33 vdd33 phyutxcl k phyutxad dr[2] phyutxad dr[0] ui/pd g h atmutxd ata[12] atmutxd ata[9] atmutxd ata[6] atmutxd ata[2] vdd33 vdd33 phyutxad dr[3] ui/pd ui/pd ui/pd h j atmutxd ata[15] atmutxd ata[13] atmutxd ata[10] atmutxd ata[7] vdd18 vdd18 ui/pd ui/pd ui/pd ui/pd j k atmutxad dr[3] atmutxad dr[1] atmutxd ata[14] atmutxd ata[11] vdd18 vdd18 vdd18 vdd33 vss vss vdd33 vdd18 vdd18 vdd18 ui/pd ui/pd ui/pd ui/pd k l memctrl_ adsc* atmutxad dr[4] atmutxad dr[2] atmutxad dr[0] vdd33 vdd18 vss vss vss vss vss vss vdd18 vdd33 ui/pd ui/pd ui/pd phyutxda ta[15] l m memdata[ 0] memctrl_ oe* memctrl_ we* atmutxcl k vdd33 vdd33 vss vss vss vss vss vss vdd33 vdd33 ui/pd phyutxda ta[14] vdd33 phyutxda ta[12] m n memdata[ 3] memdata[ 2] memdata[ 1] memctrl_ ce* vss vss vss vss vss vss vss vss vss phyutxda ta[13] phyutxda ta[11] phyutxda ta[10] vss phyutxda ta[9] n p memdata[ 4] memdata[ 5] memdata[ 6] memdata[ 7] memdata[ 9] vss vss vss vss vss vss vss vss vss microaddr [8] microaddr [10] microaddr [11] phyutxda ta[8] p r memdata[ 8] vss memdata[ 10] memdata[ 12] vdd33 vdd33 vss vss vss vss vss vss vdd33 microclk microaddr [4] microaddr [6] microaddr [7] microaddr [9] r t memdata[ 11] memdata[ 13] memdata[ 14] memaddr[ 1] vdd33 vdd18 vss vss vss vss vss vss vdd18 vdd33 reset* microaddr [1] microaddr [3] microaddr [5] t u memdata[ 15] memaddr[ 0] memaddr[ 3] memaddr[ 6] vdd18 vdd18 vdd18 vdd33 vss vss vdd33 vdd18 vdd18 vdd18 microdata [5] vdd33 microaddr [0] microaddr [2] u v memaddr[ 2] memaddr[ 4] memaddr[ 7] memaddr[ 10] vdd18 vdd18 microdata [1] microdata [4] microdata [7] mcs* v w memaddr[ 5] memaddr[ 8] memaddr[ 11] memaddr[ 14] vdd33 vdd33 mrd* microdata [0] microdata [3] microdata [6] w y memaddr[ 9] memaddr[ 12] memaddr[ 15] memaddr[ 17] vdd33 vdd33 ui/pd mrdy mwr* microdata [2] y aa memaddr[ 13] memaddr[ 16] memaddr[ 19] nc vss vss ui/pd ui/pd ui/pd microint* aa ab memaddr[ 18] memctrl_ clk statout[0] nc vss vss vdd33 vdd33 vdd18 vdd18 vdd33 vdd33 phyurxd ata[0] vss vdd33 vdd33 vdd18 vdd18 vdd33 vdd33 vss vss ui/pd ui/pd ui/pd ui/pd ab ac extmems el nc vss vgg testenabl e[1] uo uio/pd ui/pd ui/pd uo uio/pd phyurxd ata[1] phyurxd ata[5] phyurxd ata[10] phyurxd ata[15] phyurxad dr[4] ui/pd ui/pd ui/pd ui/pd phyutxda ta[2] nc phyutxda ta[7] ui/pd ui/pd ui/pd ac ad statout[1] 8khzin phyintfcs el scanenab le uo uio/pd ui/pd ui/pd ui/pd phyurxs oc uo phyurxen b[1]* phyurxd ata[4] phyurxd ata[9] phyurxd ata[13] phyurxad dr[1] phyutxprt y ui/pd ui/pd ui/pd ui/pd phyutxda ta[3] phyutxda ta[6] vss ui/pd ui/pd ad ae onesecio tristate msyncmo de uo uio/pd ui/pd ui/pd ui/pd phyurxpr ty uo uio/pd vss phyurxd ata[2] phyurxd ata[8] phyurxd ata[12] phyurxad dr[0] phyurxad dr[3] phyutxs oc ui/pd ui/pd ui/pd ui/pd phyutxda ta[1] vdd33 ui/pd ui/pd ae af testenabl e[0] uo uio/pd ui/pd ui/pd ui/pd ui/pd phyurxcl av[0] phyurxcl av[1] uo phyurxen b[0]* phyurxd ata[3] phyurxd ata[6] phyurxd ata[7] phyurxd ata[11] phyurxd ata[14] phyurxad dr[2] phyurxcl k ui/pd ui/pd ui/pd ui/pd phyutxda ta[0] phyutxda ta[4] phyutxda ta[5] ui/pd af 2625242322212019181716151413121110987654321 jtag/factory test unused output (output in tristate) (in phy-side utopia mode) phy utopia tx atm utopia rx unused input intenally pulled down (in phy-side utopia mode) phy utopia rx atm utopia tx unused i/o (internally pulled down when in input mode, output tristate) (in phy-side utopia mode) external memory microprocessor
28529-dsh-001-k mindspeed technologies ? 275 mindspeed proprietary and confidential 4.0 appendices 4.1 ima version 1.1 pics proforma to evaluate conformance of a particular implementation, it is necessary to have a statement of which capabilities and options have been implemented for a given protocol. such a statement is called a protocol implementation conformance statement (pics). 4.1.1 scope this annex provides the pics proforma for the inverse multiplexing for atm (ima) version 1.1 specification as described in af-phy-0086.001[a-1] in compliance with the relevant requirements, and in accordance with the relevant guidelines, given in iso/iec 9646-2[a-3]. 4.1.2 definitions this document uses the following terms defined in iso/iec 9646-1[a-2]: a protocol implementation conformance statement (p ics) is a statement made by the supplier of an implementation or a syste m, stating which capabilities have bee n implemented for a given protocol, a pics proforma is a document in the form of a qu estionnaire, designed by the protocol specifier or the conformance test suite specifier, which when completed for an implementation or a system, becomes the pics, and a static conformance review is a review of the extent to which the static conformance requirements are met by the implementation, accomplished by comparing the pics with the static conformance requirements expressed in the relevant protocol specification. 4.1.3 symbols and conventions m?mandatory o?option (may be selected to suit the implementation, provided that any requirements applicable to the options are observed) 4.1.4 conformance the supplier of a protocol implementation, which is claimed to conform to af-phy-0086.001[a-1], is required to complete a copy of the pics proforma provided in the following sections of this annex and is required to provide the information necessary to identify both the supplier and the implementation.
appendices 28529-dsh-001-k mindspeed technologies ? 276 mindspeed proprietary and confidential 4.1.5 ima pics proforma 4.1.5.1 global statement of conformance the implementation described in this pics proforma meets all of the mandatory requirements of the protocol specification. yes__ xx no__ note: answering ?no? indicates non-conformance to the protocol specification. non-supported mandatory capabilities are to be identified in the following tables, with an explanation in the ?comments? section of each table as to why the implementation is ?non conforming?. 4.1.5.2 instructions for completing the pics proforma each question in this section refers to a major function of the protocol. answering ?y es? to a particular question states that the implementation supports all of the mandatory procedures for that function, as defined in the referenced section of af-phy-0086.001[a-1]. answering ?no? to a particular question in this section states that the implementation does not support that function of the protocol. a supplier may also provide additional information, categorized as exceptional (x) or supplementary information. this additional information should be provided in the support column as items labeled x for exceptional or s for supplementary information, respectively for cross-re ference purposes, where is any unambiguous number. 4.1.5.3 i ma protocol functions table 4-1. basic ima protocol (bip) definition functions (1 of 5) item protocol feature cond. for status status pred. ref. support bip.1 does the implementation support a number n (1 n 32) of transmission links within an ima group operating at the same nominal link cell rate (lcr)? m(r-1) yes x no__ bip.2 does the implementation support the ima interface connected to another interface over clear channel facilities (implies cells generated by transmit ima shall only be terminated at the receive ima)? m(r-2) yes x no__ bip.3 does the interface specific tc sublayer of the implementation pass all cells to the ima sublayer or provide an i ndication that a cell was received (this includes hec errored cells)? m(r-3) yes x no__ bip.4 does the implementation prohibit cell rate decoupling at the interface specific tc sublayer? m(r-4) yes x no__ bip.5 does the implementation assign a lid unique within the ima group to each tx ima link on each physical link? m(r-5) yes x no__ bip.6 does the implementation ensure that the lid does not change while the link is a member of the ima group? m(r-6) yes x no__ bip.7 does the implementation distribute atm cells arriving from the atm layer over the n links in a cyclic round-robi n fashion, and on a cell-by-cell basis? m(r-7) yes x no__ bip.8 does the implementation distribute atm cells over the links using an ascending order based on the lid assigned to each link within the ima group? m(r-8) yes x no__
appendices 28529-dsh-001-k mindspeed technologies ? 277 mindspeed proprietary and confidential bip.9 does the implementation support the icp cell format defined in table 2 on page 31 to convey ima configuration, synchronization, status, and defect information to the far-end? m(r-9) yes x no__ bip.10 does the implementation perform cell rate decoupling by inserting ima filler cells in place of atm cells when ther e is no cell available at the atm layer? m (r-10) yes x no__ bip.11 does the implementation accept, on receive, atm cells from the n links according to ascending order based on th e lid received in the icp cells on the incoming link? m (r-11) yes x no__ bip.12 does the implementation, on receive, co mpensate for link differential delays and rebuild the origin al atm cell stream? m (r-11) yes x no__ bip.13 does the implementation discard recei ved filler cells and cells with bad hec? m (r-11) yes x no__ bip.14 does the implementation process and discard incoming icp cells? m (r-11) yes x no__ bip.15 does the implementation aggregate, on receive, the atm cell stream to the atm layer? m (r-11) yes x no__ bip.16 does the implementation preserve the order of incoming cells? m (r-11) yes x no__ bip.17 does the implementation use the icp cell to maintain ima protocol synchronization? m (r-12) yes x no__ bip.18 does the implementation use the icp cell to maintain link delay synchronization? m (r-12) yes x no__ bip.19 does the implementation transmit firs t the most significant bit of each octet of the ima oam cell? m (r-13) yes x no__ bip.20 does the implementation support the same cell header for both the filler and icp cell formats as defined in table 1 on page 28 and table 2 on page 31? m (r-14) yes x no__ bip.21 does the implementation use bit 7 of octet 7 (cid field) of the filler and icp cells to identify the ima oam cell as an icp or filler cell? m (r-15) yes x no__ bip.22 does the implementation use octets 52-53 as specified in itu-t recommendation i.610 [a-5] for octets 52-53 of the oam cells of the f1/f3 flows? m (r-16) yes x no__ bip.23 does the implementation support the filler cell format defined in table 1 on page 28? m (r-17) yes x no__ bip.24 does the implementation support the icp cell format defined in table 2 on page 31? m (r-18) yes x no__ bip.25 does the implementation transmit the content of the link specific fields appearing in class a over the link for which these fields apply? m (r-19) yes x no__ bip.26 does the implementation transmit th e same content of fields appearing in classes b and c of the icp cell over all links within an ima group? m (r-20) yes x no__ bip.27 does the implementation use the lid bits (bits 4-0 of octet 7) in the icp cell to identify the link id (range being 0 to 31)? m (r-21) yes x no__ bip.28 does the implementation use the ?tx st ate? field, located in the link ?x? information field in an icp cell, to report the transmit state of the ima link on which the ne ima is transmitting icp cells carrying lid = ?x? (?x? being a value between 0 and 31)? m (r-22) yes x no__ table 4-1. basic ima protocol (bip) definition functions (2 of 5) item protocol feature cond. for status status pred. ref. support
appendices 28529-dsh-001-k mindspeed technologies ? 278 mindspeed proprietary and confidential bip.29 does the implementation use t he ?rx state?, located in the link ?x? information field in an i cp cell, to report the receive state of the incoming ima link on which the fe ima is tr ansmitting icp cells carrying lid = ?x? (?x? being a value between 0 and 31)? m (r-23) yes x no__ bip.30 does the implementation use t he ?rx defect indicat ors? field, located in the link ?x? information field in an icp cell, to report the rx defect indicators corresponding to the incoming ima link on which the fe ima is transmitting icp cells carrying lid = ?x ? (?x? being a value between 0 and 31)? m (r-24) yes x no__ bip.31 does the implementation always transmit icp cells with octet 50 unused and set to ?0x6a? as defined in itu-t recommendation i.432 [a-4]? m (r-25) yes x no__ bip.32 does the implementation reserve the end-to-end channel field (octet 51) as a proprietary channel? m (r-26) yes x no__ bip.33 does the implementation set the end-to-end channel field (octet 51) to ?0? when not using this field? m (r-27) yes x no__ bip.34 does the implementation not rely on the processing of the end-to-end channel field for any ima functionality? m (r-28) yes x no__ bip.35 does the implementation only consid er the information within icp cells exhibiting neither a hec nor a crc-10 error? m (r-29) yes x no__ bip.36 does the implementation always transmit "0x03" over the oam label in the filler and icp cells? m (r-30) yes x no__ bip.37 if the implementation does not support the ima version proposed by the oam label received from the far-end ima unit, does the implementation report the ?config-aborted - unsupported ima version" state over the ?group status and control? field? m (r-31) yes x no__ bip.38 does the implementation transmit ima frames, composed of m consecutive cells, on each link within the ima group? m (r-32) yes x no__ bip.39 does the implementation send icp cel ls on each link once per ima frame, hence every m cells? m (r-33) yes x no__ bip.40 does the implementation use the ifsn field in the icp cell to indicate the sequence number of the ima frame? m (r-34) yes x no__ bip.41 does the implementation increment the ifsn field in the icp cell from 0 to 255 and repeat the sequence? m (r-35) yes x no__ bip.42 does the implementation increment the ifsn field in the icp cell with each ima frame on a per-link basis? m (r-36) yes x no__ bip.43 within an ima frame, does the impl ementation place identical ifsn values in the icp cells sent on each link? m (r-36) yes x no__ bip.44 does the implementation align the tr ansmission of the ima frame on all links within an ima group? m (r-37) yes x no__ bip.45 does the implementation use the icp cell offset field (octet 9) to indicate the location of the icp cell within the ima frame of length m cells? m (r-38) yes x no__ bip.46 does the implementation always set th e value of the icp cell offset between 0 and m-1 where m is the ima frame length in cells? m (r-39) yes x no__ bip.47 does the implementation distribute the i cp cells, from link to link within the ima group, in an uniform fashion across the ima frame? o(o-1) yes x no__ table 4-1. basic ima protocol (bip) definition functions (3 of 5) item protocol feature cond. for status status pred. ref. support
appendices 28529-dsh-001-k mindspeed technologies ? 279 mindspeed proprietary and confidential bip.48 does the implementation select the of fset of the icp cell sent of any link when the link is assigned a lid? m (r-40) yes x no__ bip.49 does the implementation retain the o ffset of the icp cell sent on a given link until the link is no longer part of the group? m (r-40) yes x no__ bip.50 does the implementation always use th e frame length field in the icp cell to indicate the value of m? m (r-41) yes x no__ bip.51 does the implementation support m = 128? m (r-42) yes x no__ bip.52 does the implementation support m = 32? o (o-2) yes x no__ bip.53 does the implementation support m = 64? o (o-2) yes x no__ bip.54 does the implementation support m = 256? o (o-2) yes x no__ bip.55 does the implementation only change the value m at group start-up time? m (r-43) yes x no__ bip.56 does the implementation use on transmit the val ue configured by the um? (o-2) m (cr-1) yes x no__ bip.57 does the implementation allow diff erent values of m in both tx and rx directions? (o-2) m (cr-2) yes x no__ bip.58 does the implementation synchronize its incoming links using the received m value for ima frame synchronization? (o-2) m (cr-3) yes x no__ bip.59 does the implementation abort the start-up procedure using the corresponding code in the group status and control field of the icp cell when it does not support the received m? m (r-44) yes x no__ bip.60 does the implementation allow to configure the value m? o (o-3) yes x no__ bip.61 does the implementation set the scc i field to the previously transmitted scci field value, incremented modulo 256, to indicate a change on at least one of the fields appearing in octets 12 through 49 in the transmitted icp cell? m (r-45) yes x no__ bip.62 does the implementation use the scci fi eld to identify r eceived icp cells for processing when icp cells are monitored on more than one link, or when the monitored link has changed? m (r-46) yes x no__ bip.63 does the implementation process the fields in octets 12 through 49 if the scci field has advanced beyond the scci value of the last processed icp cell? m (r-46) yes x no__ bip.64 does the implementation select the ima id at group start-up time? m (r-47) yes x no__ bip.65 does the implementation transmit the im a id in the ima id field? m (r-48) yes x no__ bip.66 does the implementation allow to conf igure the value of ima id? o (o-4) yes x no__ bip.67 does the implementation use the ?gr oup symmetry mode? field, specified in table 2 on page 31, to indicate the symmetry of the ima group? m (r-49) yes x no__ bip.68 does the implementation ensure that the symmetry of the group is only established or changed at group start-up time? m (r-50) yes x no__ bip.69 does the implementation support the symmetrical configuration and operation mode? m (r-51) yes x no__ bip.70 does the implementation support the symmetrical configuration and asymmetrical operation mode? o (o-5) yes x no__ table 4-1. basic ima protocol (bip) definition functions (4 of 5) item protocol feature cond. for status status pred. ref. support
appendices 28529-dsh-001-k mindspeed technologies ? 280 mindspeed proprietary and confidential bip.71 does the implementation support the asymmetrical configuration and operation mode? o(o-6) yes x no__ bip.72 does the implementation abort the start-up procedure using the appropriate code defined in the ?group status and control? field of the icp cell (as specified in table 2 on page 31) if the ne does not support the symmetry mode proposed by the fe? m (r-52) yes x no__ bip.73 does the implementation abort the start-up procedure using the appropriate code defined in the ?group status and control? field of the icp cell (as specified in table 2 on page 31) if the symmetry mode proposed by the fe and the configured symmetry mode of the ne do not match? m (r-52) yes x no__ bip.74 in order to allow a fast recovery when (o-5) or (o-6) is used at the ne and when the fe ima unit can only be configured to the ?symmetrical configuration and operation? mode, does the implementation adjust to ?symmetrical configuration and operation?. o(o-7) yes x no__ bip.75 does the implementation support only the valid combinations of group symmetry modes at each end of the ima virtual link as specified in table 4 on page 36? m (r-53) yes x no__ bip.76 does the implementation allow configuration of the group mode? o (o-8) yes x no__ comments: maximum group size is 8 links. table 4-2. qos requirements functions item protocol feature cond. for status status pred. ref. support qos.1 does the implementation support all atm traffic/qos classes supported by the atm layer? m (r-54) yes x no__ comments: table 4-3. ctc and itc operation functions (1 of 2) item protocol feature cond. for status status pred. ref. support cit.1 does the implementation indicate to th e fe in which transmit clock mode it is running in the ?transmit cl ock mode? field in the icp cell? m (r-55) yes x no__ cit.2 does the implementation support the ctc mode in the transmit direction? m (r-56) yes x no__ cit.3 does the implementation only indicate to the fe that it is in the ctc mode when all the ?transmit? clocks of the links in the group are derived from the same source? m (r-57) yes x no__ cit.4 does the implementation support the itc m ode in the transmit direction? o (o-9) yes x no__ cit.5 does the implementation indicate that it is in the itc mode even if all the transmit clocks of the links in the group are derived from the same source? o (o-10) yes x no__ cit.6 does the implementation use the ce ll stuffing procedure to prevent link transmit buffer under-run or over-run? (o-9) m (cr-4) yes x no__ cit.7 does the implementation indicate a stuff event in the icp cell preceding a stuff event using the mandatory lsi c odes specified in table 2 on page 30? m (r-58) yes x no__ table 4-1. basic ima protocol (bip) definition functions (5 of 5) item protocol feature cond. for status status pred. ref. support
appendices 28529-dsh-001-k mindspeed technologies ? 281 mindspeed proprietary and confidential cit.8 does the implementation perform stuffing by repeat ing the icp cell containing the lsi code indicating that ?this cell is 1 out of 2 icp cells comprising the stuff event?? m (r-59) yes x no__ cit.9 does the implementation also indicate an incoming stuff event in the fourth, third, and second icp preceding the stuff event using the optional lsi codes? o (o-11) yes x no__ cit.10 at any given link, does the implementation ensure it does not introduce a stuff event more than once every 5*m icp, filler and atm layer cells? m (r-60) yes x no__ cit.11 does the implementation remove one of any two consecutive icp cells with lsi code indicating ?this cell is 1 out of the 2 icp cells comprising the stuff event?? m (r-61) yes x no__ cit.12 does the implementation ensure that the sicp cell is not counted as a cell for the purposes of determining the ima round-robin sequence? m (r-61) yes x no__ cit.13 does the implementation support ctc and itc modes on receive? m (r-62) yes x no__ cit.14 does the implementation inform the um of a mismatch between the fe and ne ima transmit clock modes? m (r-63) yes x no__ cit.15 does the implementation ensure th at a restart is not caused if the implementation detects a mismatch between the fe and ne transmit clock modes? m (r-63) yes x no__ cit.16 does the implementation rely on at least one icp cell with a correct crc-10 in order to process the incoming stuff cell indication code (this is recommended)? o (o-12) yes x no__ comments: table 4-4. ima data cell (idc) rate implementation functions (1 of 2) item protocol feature cond. for status status pred. ref. support idc.1 does the implementation ensure on transm it that a filler cell is not injected if an atm layer cell is available for scheduling? m (r-64) yes x no__ idc.2 does the implementation only check on transmit that an atm layer cell is available and accept that cel l only when the tx idcc ticks? m (r-64) yes x no__ idc.3 does the implementation only select the trl from the set of links whose transmit state is active? m (r-65) yes x no__ idc.4 if there is no link in the active stat e, does the implementation select one of the links in the usable state, if any, or one of the links in the unusable state otherwise? m (r-66) yes x no__ idc.5 does the implementation only select or change the trl during the following situations: during group start-up, when the previously selected trl's transm it state changes from active to any other state (e.g., usable, unusable, or not in group) while another link?s transmit state is active, or when the previously selected trl?s transmit state changes from usable to unusable or not in group while another link?s transmit state is active or usable? m (r-67) yes x no__ table 4-3. ctc and itc operation functions (2 of 2) item protocol feature cond. for status status pred. ref. support
appendices 28529-dsh-001-k mindspeed technologies ? 282 mindspeed proprietary and confidential idc.6 does the implementation indicate the selected or changed trl to the fe over the ?transmit timing informat ion? field in the icp cell? m (r-68) yes x no__ idc.7 does the implementation derive the tx idcc from the selected trl according to equation 1 on page 40? m (r-69) yes x no__ idc.8 when running in the ctc mode, does the implementation introduce a stuff event every 2048 icp, filler and atm layer cells on all links? m (r-70) yes x no__ idc.9 does the implementation introduce a stuff event every 2048 icp, filler and atm layer cells on the trl? (o-9) m (cr-5) yes x no__ idc.10 does the implementation introduce st uff events on links other than the trl in order to compensate for the timi ng difference between the trl and the other links? (o-9) m (cr-6) yes x no__ idc.11 does the implementation remove cdv at tributed to the presence of icp cells by a mechanism equivalent to providing a small smoothing buffer into which cells are placed after reordering and after removing icp cells? m (r-71) yes x no__ idc.12 if the trl is in the working state and the fe has, for at least 100 milliseconds, identified a given link as the trl, does the implementation derive the rx idcr using the incoming link indicated by the fe as the trl? m (r-72) yes x no__ idc.13 does the implementation have an equival ent behavior to the following: when the ima data cell clock at the receiver ticks, one cell is removed from the smoothing buffer; if the cell is a filler cell, then the filler cell is discarded and nothing passed to the atm layer; if the cell is not a filler cell, then it is passed to the atm layer? m (r-73) yes x no__ comments: table 4-5. link differen tial delay (ldd) functions item protocol feature cond. for status status pred. ref. support ldd.1 does the implementation introdu ce a differential delay among the constituent links of a maximum of 2.5 cell times at the physical link rate? m (r-74) yes x no__ ldd.2 does the implementation tolerate up to at least 25 milliseconds of link differential delay on receive? m (r-75) yes x no__ ldd.3 does the implementation allow conf iguring the link di fferential delay tolerance? o (o-13) yes x no__ comments: table 4-6. ima interface operation (iio) functions (1 of 4) item protocol feature cond. for status status pred. ref. support iio.1 does the implementation support the tx lsm defined in table 8 on page 52? m (r-76) yes x no__ iio.2 does the implementation support the rx lsm defined in table 9 on page 53? m (r-77) yes x no__ iio.3 does the implementation signal the current state of the tx lsm to the fe ima unit via the icp cells? m (r-78) yes x no__ table 4-4. ima data cell (idc) rate implementation functions (2 of 2) item protocol feature cond. for status status pred. ref. support
appendices 28529-dsh-001-k mindspeed technologies ? 283 mindspeed proprietary and confidential iio.4 does the implementation perform the actions corresponding to the tx lsm sub-states? m (r-78) yes x no__ iio.5 does the implementation update the tx lsm according the occurrence of the events listed in table 8 on page 52? m (r-78) yes x no__ iio.6 does the implementation treat sequent ially the incoming events that trigger the tx lsm, although the order of tr eatment is implemen tation specific if these events appear simultaneously? m (r-78) yes x no__ iio.7 does the implementation signal the current state of the rx lsm to the fe ima unit via the icp cells? m (r-78) yes x no__ iio.8 does the implementation perform the actions corresponding to the rx lsm sub-states? m (r-78) yes x no__ iio.9 does the implementation update the rx lsm according the occurrence of the events listed in table 9 on page 53? m (r-78) yes x no__ iio.10 does the implementation treat sequent ially the incoming events that trigger the rx lsm, although the order of treatme nt is implementation specific if these events appear simultaneously? m (r-78) yes x no__ iio.11 does the implementation report any change of the tx and rx lsms within the next 2*m (where m is the m used by the ima transmi tter) cells on that link over the ?tx state? and ?rx state? fields of the link information field (refer to table 3 on page 32)? m (r-79) yes x no__ iio.12 does the implementation use one of the unusable encodings when reporting the unusable state? m (r-80) yes x no__ iio.13 does the implementation use ?inhibited?, ?failed?, ?fault? or ?mis- connected? as a reason when reporting the unusable state? o (o-14) yes x no__ iio.14 does the implementation re-evaluate the tx and rx lsms state upon each incoming icp cell with new state indication? m (r-81) yes x no__ iio.15 does the implementation allow the valid combinations of tx and rx lsm states and disallow the invalid combinations when running in the symmetrical configuration and operation mode? m (r-82) yes x no__ iio.16 does the implementation allow the valid combinations of tx and rx lsm states and disallow the invalid combinations when running in the symmetrical configuration and asymmetrical operation mode? m (r-82) yes x no__ iio.17 does the implementation allow all co mbinations of tx and rx lsm states when running in the asymmetrical configuration and operation mode? m (r-82) yes x no__ iio.18 does the implementation report any gsm states, with the exception of the not configured state, to the fe group using the corresponding value defined in the ?group status and control? field? m (r-83) yes x no__ iio.19 does the implementation always send over each link the same value in the ?group status and control? field fo r at least 2 consecutive ima frames? m (r-84) yes x no__ iio.20 does the implementation validate the rx oam label, rx m, and rx ima id over at least one link before mo ving into the start-up-ack state? m (r-85) yes x no__ iio.21 does the implementation use the valid ated rx oam label, rx m, and rx ima id to achieve ima frame synchronization as defined in section 11 on page 68? m (r-86) yes x no__ table 4-6. ima interface operation (iio) functions (2 of 4) item protocol feature cond. for status status pred. ref. support
appendices 28529-dsh-001-k mindspeed technologies ? 284 mindspeed proprietary and confidential iio.22 does the implementation ensure that at least p tx links in the transmit direction and p rx links in the received direction can be moved into the active state before moving the gsm into the operational state? m (r-87) yes x no__ iio.23 does the implementation ensure that p tx is greater than zero? m (r-88) yes x no__ iio.24 does the implementation ensure that p rx is greater than zero? m (r-88) yes x no__ iio.25 does the implementation ensure that p tx and p rx are equal when the configured in the symmetrical configuration and operation mode? m (r-89) yes x no__ iio.26 does the implementation allow configuration of the value of p tx ? o (o-15) yes x no__ iio.27 does the implementation allow configuration of the value of p rx ? o (o-15) yes x no__ iio.28 does the implementation report the config-aborted state for at least one second when the configuration requested by the fe is unacceptable? m (r-90) yes x no__ iio.29 does the implementation support the gsm state transitions as defined in 13 on page 60? m (r-91) yes x no__ iio.30 does the implementation determine an d report that the group is up when both the local and remote gsms are operational? m (r-92) yes x no__ iio.31 does the implementation determine a nd report that the group is down when either the local or the remote gsm is not operational? m (r-92) yes x no__ iio.32 does the implementation report the proper reasons why the gsm is not operational? m (r-92) yes x no__ iio.33 does the implementation report the highest priority reason according to table 14 on page 61? m (r-92) yes x no__ iio.34 does the implementation report the entrance of the gtsm into the down state to the um and atm layer management? m (r-93) yes x no__ iio.35 is the report of the entrance of the gtsm into the down state the only notification to the atm layer manageme nt about physical layer defects or failures? m (r-93) yes x no__ iio.36 does the implementation report the return of the gtsm to the up state to the um and atm layer management? m (r-94) yes x no__ iio.37 does the implementation ensure it does not drop any atm layer cells when adding or recovering links while the gs m is maintained in the operational state? m (r-95) yes x no__ iio.38 does the implementation ensure that it does not drop any atm layer cells when deleting or inhibiting links while the gsm is maintained in the operational state? m (r-96) yes x no__ iio.39 when running the group start-up procedure, does the implementation ensure that all accepted links have thei r states changed to tx=usable in the same update of the icp cell? m (r-97) yes x no__ iio.40 when running the group start-up pro cedure and after the tx state of all accepted links has been reported in a previous update of the icp cell, does the implementation ensure that all accepted links have their states changed to rx=active in the same update of the icp cell? m (r-98) yes x no__ iio.41 when running the group start-up pro cedure and after the rx state of all accepted links has been reported in a previous update of the icp cell, does the implementation ensure that all accepted links have their states changed to tx=active in the same update of the icp cell? m (r-99) yes x no__ table 4-6. ima interface operation (iio) functions (3 of 4) item protocol feature cond. for status status pred. ref. support
appendices 28529-dsh-001-k mindspeed technologies ? 285 mindspeed proprietary and confidential iio.42 when running the group start-up proce dure, does the implementation wait a minimum of one second, unless all the c onfigured links are being reported tx=usable by fe, before reporting links rx=active? m (r-100) yes x no__ iio.43 when running the group start-up proce dure, does the implementation wait a minimum of one second, unless all the c onfigured links are being reported rx=active by fe, before reporting links tx=active? m (r-101) yes x no__ iio.44 does the implementation synchroni ze the insertion of new links or recovered links added using the slow recovery mechanism, defined in section 12.1.3.1 on page 74, within the ima rr? m (r-102) yes x no__ iio.45 does the implementation execute only one lasr procedure per ima group at any time (even if more than one link is inserted at the same time)? m (r-103) yes x no__ iio.46 does the implementation delay the in sertion of one or more new links or a possible slow link recovery when the lasr is in progress until the link addition procedure is completed or aborted? m (r-104) yes x no__ iio.47 when running the lasr procedure, does the implementation ensure that all the inserted links have their states changed to tx=usable in the same update of the icp? m (r-105) yes x no__ iio.48 when running the lasr procedure and after the tx state of all accepted links has been reported usable in a previous update of the icp cell, does the implementation ensure that all the in serted links have their states changed to rx=active in the same update of the icp cell? m (r-106) yes x no__ iio.49 when running the lasr procedure an d after the rx state of all accepted links has been reported active in a previous update of the icp cell, does the implementation ensure that all the in serted links have their states changed to tx=active in the same update of the icp cell? m (r-107) yes x no__ iio.50 when running the lasr procedur e, does the implementation wait a minimum of one second, unless all the inserted links are being reported tx=usable by fe, before reporting links rx=active? m (r-108) yes x no__ iio.51 when running the lasr procedur e, does the implementation wait a minimum of one second, unless the inserted links are being reported rx=active by fe, before reporting links tx=active? m (r-109) yes x no__ table 4-7. ima frame synchronization (ifs) mechanism functions (1 of 2) item protocol feature cond. for status status pred. ref. support ifs.1 does the implementation perform ima frame synchronization on each link, based on the ifsm defined in figure 19 on page 69 and table 16 on page 69? m (r-110) yes x no__ ifs.2 does the implementation operate the ifsm for each link independently of any link defects and link delay compensation? m (r-111) yes x no__ ifs.3 does the implementation support the default value 2 for alpha( )? m (r-112) yes x no__ ifs.4 does the implementation support the default value 2 for beta( )? m (r-112) yes x no__ ifs.5 does the implementation support the default value 1 for gamma( )? m (r-112) yes x no__ ifs.6 does the implementation support the value 1 for alpha( )? o (o-16) yes x no__ table 4-6. ima interface operation (iio) functions (4 of 4) item protocol feature cond. for status status pred. ref. support
appendices 28529-dsh-001-k mindspeed technologies ? 286 mindspeed proprietary and confidential ifs.7 does the implementation support the value 1 for beta( )? o (o-16) yes x no__ ifs.8 does the implementation support the value 3 for beta( )? o (o-16) yes x no__ ifs.9 does the implementation support the value 4 for beta( )? o (o-16) yes x no__ ifs.10 does the implementation support the value 5 for beta( )? o (o-16) yes x no__ ifs.11 does the implementation support the value 2 for gamma( )? o (o-16) yes x no__ ifs.12 does the implementation support the value 3 for gamma( )? o (o-16) yes x no__ ifs.13 does the implementation support the value 4 for gamma( )? o (o-16) yes x no__ ifs.14 does the implementation support the value 5 for gamma( )? o (o-16) yes x no__ ifs.15 does the implementation assume that any occurrence of hec/crc errored cell in the icp cell position was an icp cell? m (r-113) yes x no__ ifs.16 does the implementation ignore the cell content of a hec/crc errored cell in the icp cell position? m (r-113) yes x no__ ifs.17 does the implementation go into the hunt state from any other state when no longer getting cells from the physical layer? o (o-17) yes x no__ ifs.18 does the implementation maintain im a frame synchronization for cases 1, 2, 3, and 6 identified in figure 20 on page 71? m (r-114) yes x no__ ifs.19 does the implementation maintain ima frame synchronization for case 4 identified in figure 20 on page 71? o (o-18) yes x no__ need (o-11) ifs.20 does the implementation maintain ima frame synchronization for case 5 identified in figure 20 on page 71? o (o-18) yes x no__ ifs.21 does the implementation maintain ima frame synchronization for case 7 identified in figure 20 on page 71 wh en passing stuff indication over more than one of the previous icp cells and when beta( ) is greater than 2? o (o-19) yes x no__ need (o-11) comments: (o-11) required to support (o-18) and (o-19). table 4-8. ima interface oam operation functions (1 of 5) item protocol feature cond. for status status pred. ref. support oam.1 does the implementation report the following link remote defect indicators: link defects, lif, and lods? m (r-115) yes x no__ oam.2 if several defects are detected at the same time, does the implementation report the defect with the highest priority , as listed in table 17 on page 72? m (r-116) yes x no__ oam.3 does the implementation report any rx defect to the far-end ima within the next 2*m cells to be transmitted after the defect state has been entered as specified in section 12.1.3 on page 72 (where m is the m used by the ima transmitter)? m (r-117) yes x no__ oam.4 does the implementation perform error handling as specified in figure 21 on page 73 and figure 22 on page 74? m (r-118) yes x no__ oam.5 on a given link, does the implementati on pass to the atm layer from the ima sublayer any cells accumulated before the occurrence of an ocd or oif anomaly on that link? m (r-119) yes x no__ table 4-7. ima frame synchronization (ifs) mechanism functions (2 of 2) item protocol feature cond. for status status pred. ref. support
appendices 28529-dsh-001-k mindspeed technologies ? 287 mindspeed proprietary and confidential oam.6 does the implementation inhibit the passing from the ima sublayer to the atm layer of any cells received on a link during an ocd or oif anomaly condition reported on that link? m (r-120) yes x no__ oam.7 does the implementation replace with fi ller cells all atm layer cells received on a link after an ocd or oif anomaly condition has been detected on that link? m (r-121) yes x no__ oam.8 does the implementation only report an rx defect in the backward direction after lif or lods def ect state is entered? m (r-122) yes x no__ oam.9 does the implementation report the lif or lods defect as specified in section 12.1.2 on page 72? m (r-123) yes x no__ oam.10 does the implementation detect erro red icp cells as indicated in table 18 on page 77? m (r-124) yes x no__ oam.11 does the implementation detect invalid icp cells as indicated in table 18 on page 77? m (r-124) yes x no__ oam.12 does the implementation detect missi ng icp cells as indicated in table 18 on page 77? m (r-124) yes x no__ oam.13 does the implementation report oif events as indicated in table 18 on page 77? m (r-124) yes x no__ oam.14 does the implementation report lif de fects as indicated in table 18 on page 77? m (r-124) yes x no__ oam.15 does the implementation report lods defects as indicated in table 18 on page 77? m (r-124) yes x no__ oam.16 does the implementation report rdi- ima defects as indicated in table 18 on page 77? m (r-124) yes x no__ oam.17 does the implementation increment iv-ima for every detected errored, invalid or missing icp cel l, except during seconds when a ses-ima or uas- ima condition is reported, as indicated in table 19 on page 77? m (r-125) yes x no__ oam.18 does the implementation increment oi f-ima for each reported oif anomaly, except during seconds when a ses-ima or uas-ima condition is reported, as indicated in table 19 on page 77? o (o-20) yes x no__ oam.19 does the implementation increment ses-ima for every one second interval containing 30% of the icp cells counted as iv-ima, as indicated in table 19 on page 77? m (r-126) yes x no__ oam.20 does the implementation increment ses-ima for every one interval of one second containing one or more link def ects (e.g., los, oof/lof, ais, and lcd), except during seconds when an uas-ima condition is reported, as indicated in table 19 on page 77? m (r-126) yes x no__ oam.21 does the implementation increment ses-ima for every one second interval containing one or more lif link defects, except during seconds when an uas-ima condition is reported, as indicated in table 19 on page 77? m (r-126) yes x no__ oam.22 does the implementation increment ses-ima for every one second interval containing one or more lods link defects, except during seconds when a uas-ima condition is reported, as indicated in table 19 on page 77? m (r-126) yes x no__ table 4-8. ima interface oam operation functions (2 of 5) item protocol feature cond. for status status pred. ref. support
appendices 28529-dsh-001-k mindspeed technologies ? 288 mindspeed proprietary and confidential oam.23 does the implementation increment ses-ima-fe for every one second interval containing one or more rdi-ima defect, except during seconds when a uas-ima-fe condition is reported, as indicated in table 19 on page 77? m (r-127) yes x no__ oam.24 does the period of ne unavailability begin at the onset of 10 contiguous ses-ima (including the first 10 seconds to enter the uas-ima condition), as indicated in table 19 on page 77? m (r-128) yes x no__ oam.25 does the period of ne unavailability end at the onset of 10 contiguous seconds with no ses-ima (excluding the last 10 seconds to exit the uas- ima condition), as indicated in table 19 on page 77? m (r-128) yes x no__ oam.26 does the implementation increment uas-ima for each one second interval when the uas-ima condition is reporte d, as indicated in table 19 on page 77? m (r-128) yes x no__ oam.27 does the period of fe unavailability begin at the onset of 10 contiguous ses- ima (including the first 10 seconds to enter the uas-ima condition), as indicated in table 19 on page 77? m (r-129) yes x no__ oam.28 does the period of fe unavailability end at the onset of 10 contiguous seconds with no ses-ima-fe (excluding the last 10 seconds to exit the uas- ima-fe condition), as indicated in table 19 on page 77? m (r-129) yes x no__ oam.29 does the implementation increment uas-ima-fe for each one second interval when the uas-ima-fe condition is reported, as indicated in table 19 on page 77? m (r-129) yes x no__ oam.30 does the implementation increment tx-uus-ima for each second when the ne tx lsm is unusable, as indicated in table 19 on page 77? m (r-130) yes x no__ oam.31 does the implementation incremen t rx-uus-ima for each second when the ne rx lsm is unusable, as indicated in table 19 on page 77? m (r-131) yes x no__ oam.32 does the implementation incremen t tx-uus-ima-fe for each second when the fe tx lsm is reported unusable, as indicated in table 19 on page 77? m (r-132) yes x no__ oam.33 does the implementation increment rx-uus-ima-fe for each second when the fe rx lsm is reported unusable, as indicated in table 19 on page 77? m (r-133) yes x no__ oam.34 does the implementation increment tx-fc each time the tx-mis-connected link failure condition is entered, as indicated in table 19 on page 77? m (r-134) yes x no__ oam.35 does the implementation increment tx -fc each time the tx-fault link failure condition is entered, as indicated in table 19 on page 77? m (r-134) yes x no__ oam.36 does the implementation increment rx-fc each time the lif link failure condition is entered, as indicated in table 19 on page 77? m (r-135) yes x no__ oam.37 does the implementation increment rx -fc each time the lods link failure condition is entered, as indicated in table 19 on page 77? m (r-135) yes x no__ oam.38 does the implementation incremen t rx-fc each time the rx-mis-connected link failure condition is entered, as indicated in table 19 on page 77? m (r-135) yes x no__ oam.39 does the implementation increment rx -fc each time the rx-fault link failure condition is entered, as indicated in table 19 on page 77? m (r-135) yes x no__ oam.40 does the implementation increment tx-fc-fe each time the tx-unusable-fe link failure condition is entered, as indicated in table 19 on page 77? o (o-21) yes x no__ table 4-8. ima interface oam operation functions (3 of 5) item protocol feature cond. for status status pred. ref. support
appendices 28529-dsh-001-k mindspeed technologies ? 289 mindspeed proprietary and confidential oam.41 does the implementation increment rx -fc-fe each time the rfi-ima link failure condition is entered, as indicated in table 19 on page 77? o (o-22) yes x no__ oam.42 does the implementation increment rx-fc-fe each time the rx-unusable-fe link failure condition is entered, as indicated in table 19 on page 77? o (o-22) yes x no__ oam.43 does the implementation incremen t tx-stuff-ima for each stuff event inserted in the transmit direction, as indicated in table 19 on page 77? o (o-23) yes x no__ oam.44 does the implementation increment rx-stuff-ima for each stuff event detected in the receive direction, except during seconds when a ses-ima or uas-ima condition is reported, as indicated in table 19 on page 77? o (o-24) yes x no__ oam.45 does the implementation increment gr-uas-ima for each second when the gtsm is down, as indicated in table 19 on page 77? m (r-136) yes x no__ oam.46 does the implementation incremen t gr-fc each time the config-aborted group failure condition is entered, as indicated in table 19 on page 77? m (r-137) yes x no__ oam.47 does the implementation increment gr-fc each time the insufficient-links group failure condition is entered, as indicated in table 19 on page 77? m (r-137) yes x no__ oam.48 does the implementation increment gr-fc-fe each time the start-up-fe group failure condition is entered, as indicated in table 19 on page 77? o (o-25) yes x no__ oam.49 does the implementation incremen t gr-fc-fe each time the config- aborted-fe group failure condition is entered, as indicated in table 19 on page 77? o (o-25) yes x no__ oam.50 does the implementation increment gr-fc-fe each time the insufficient- links-fe group failure condition is entered, as indicated in table 19 on page 77? o (o-25) yes x no__ oam.51 does the implementation increment gr-fc-fe each the blocked-fe group failure condition is entered, as indicated in table 19 on page 77? o (o-25) yes x no__ oam.52 does the implementation accumulate ima performance parameters over 15 minute intervals? o (o-26) yes x no__ oam.53 does the implementation accumulate ima performance parameters over 24 hour intervals? o (o-27) yes__ no x oam.54 does the implementation keep the current/p revious and recent data? (o-26) m (cr-7) yes x no__ oam.55 does the implementation use the current data for threshold crossing? (o-26) m (cr-8) yes__ no x oam.56 does the implementation keep the current/pr evious and recent data? (o-27) m (cr-9) yes__ no x oam.57 does the implementation use the current data for threshold crossing? (o-27) m (cr-10) yes__ no x oam.58 does the implementation report a lif failure alarm for the persistence of a lif defect at the ne? m (r-138) yes x no__ oam.59 does the implementation report a lods failure alarm for the persistence of a lods defect at the ne? m (r-139) yes x no__ oam.60 does the implementation report a rfi-ima failure alarm for the persistence of a rdi-ima defect at the ne? m (r-140) yes x no__ oam.61 does the implementation report tx-m is-connected failure alarm when the tx link is detected as mis-connected? m (r-141) yes x no__ oam.62 does the implementation report rx-m is-connected failure alarm when the rx link is detected as mis-connected? m (r-142) yes x no__ table 4-8. ima interface oam operation functions (4 of 5) item protocol feature cond. for status status pred. ref. support
appendices 28529-dsh-001-k mindspeed technologies ? 290 mindspeed proprietary and confidential oam.63 does the implementation report a tx fault failure alarm for any implementation specific tx fault declared at the ne? o (o-28) yes x no__ oam.64 does the implementation report a rx fault failure alarm for any implementation specific rx fault declared at the ne? o (o-29) yes x no__ oam.65 does the implementation report a tx -unusable-fe failure alarm when it receives tx-unusable from fe? m (r-143) yes x no__ oam.66 does the implementation report a rx-unusable-fe failure alarm when it receives rx-unusable from fe? m (r-144) yes x no__ oam.67 does the implementation report a star t-up-fe failure alarm when it receives this signal from fe (the declaration of this failure alarm may be delayed to ensure the fe remains in start-up)? m (r-145) yes x no__ oam.68 does the implementation report a conf ig-aborted failure alarm when the fe tries to use unacceptable configuration parameters? m (r-146) yes x no__ oam.69 does the implementation report a conf ig-aborted-fe failure alarm when the fe reports unacceptable configuration parameters? m (r-147) yes x no__ oam.70 does the implementation report an in sufficient-links failure alarm when less than p tx transmit links or p rx receive links are active? m (r-148) yes x no__ oam.71 does the implementation report an in sufficient-links-fe failure alarm when the fe reports that less than p tx transmit links or p rx receive links are active? m (r-149) yes x no__ oam.72 does the implementation report a bl ocked-fe failure alarm when the fe reports that it is blocked? m (r-150) yes x no__ oam.73 does the implementation report gr-tim ing-mismatch when the fe transmit clock mode is different than the ne transmit clock mode? m (r-151) yes x no__ oam.74 in the case of the lif, lods, rfi- ima and fault failure alarms, does the implementation support 2.5 0.5 seconds as a default persistence checking time to enter a failure alarm condition? m (r-152) yes x no__ oam.75 in the case of the lif, lods, rfi- ima and fault failure alarms, does the implementation support 10 0.5 seconds as a default persistence clearing time to exit the failure alarm condition? m (r-152) yes x no__ oam.76 in the case of the lif, lods, rfi-im a and fault failure alarms, does the ima allow configuration of other values fo r default persistence checking time to enter a failure alarm condition? o (o-30) yes x no__ oam.77 in the case of the lif, lods, rfi-im a and fault failure alarms, does the ima allow configuration of other values fo r default persistence checking time to exit the same failure alarm condition? o (o-30) yes x no__ oam.78 does the implementation ensure that the tx-fault failure alarm, as defined in (o-28) on page 79, is not cleared until th e fault that led to the declaration of the alarm is no longer present for the dur ation specified to clear the alarm in (r-152) on page 80? (o-28) m (cr-11) yes x no__ oam.79 does the implementation ensure that th e rx-fault failure alarm, as defined in (o-29) on page 79, is not cleared until th e fault that led to the declaration of the alarm is no longer present for the dur ation specified to clear the alarm in (r-152) on page 80? (o-29) m (cr-12) yes x no__ comments: 24 hour pm intervals require external software. no th reshold crossing feature in driv er. link fault failures are n ot defined in standard. table 4-8. ima interface oam operation functions (5 of 5) item protocol feature cond. for status status pred. ref. support
appendices 28529-dsh-001-k mindspeed technologies ? 291 mindspeed proprietary and confidential table 4-9. test pattern procedure (tpp) functions item protocol feature cond. for status status pred. ref. support tpp.1 does the implementation activate the t est pattern procedure in the transmit direction? o(o-31)yes x no__ tpp.2 does the implementation use the test link command field in the icp cell (as defined in the tx test control field in table 2 on page 31) to request the fe to activate the loop back of the test patte rn contained in the tx test pattern field? (o-31) m (cr-12) yes x no__ tpp.3 does the implementation use the tx li d field defined in the tx test control field in table 2 on page 31 to identify to the fe which transmit link the fe should extract the tx test patter n from in the received icp cells? (o-31) m (cr-12) yes x no__ tpp.4 does the implementation send any changed values of the test link command, tx lid and tx test pattern fields in icp cells for at least 2 consecutive ima frames over each link within the ima group? (o-31) m (cr-12) yes x no__ tpp.5 does the implementation continue to send the same values of the test link command, tx lid and tx test pattern fields as long a s the ima transmitter wants the fe ima unit to loop back the test pattern? (o-31) m (cr-12) yes x no__ tpp.6 does the implementation monitor the incoming icp cells on the links already recognized in the group to detect a change of the test link command? m (r-153) yes x no__ tpp.7 if the test link command field is de tected as active over the links already recognized in the group and over the test link, does the implementation copy the value of the tx test pattern field received from the test link, indicated over the tx lid field, into the rx test pattern field on every subsequent icp cell sent over all outgoing links in the group? m (r-154) yes x no__ tpp.8 does the implementation continue sending the same value over the rx test pattern field until the ima transmitte r has received an indication to stop looping the pattern, to loop a new pattern received from the same link over the tx test pattern, or to loop the t est pattern received from another link (indicated over the tx lid field)? m (r-155) yes x no__ tpp.9 does the implementation return the ?0xff? pattern over the rx test pattern field when the incoming test command is inactive or the test link is not detected? m (r-156) yes x no__ tpp.10 does the implementation only handle one test pattern per ima group at any given time? m (r-157) yes x no__ comments:
appendices 28529-dsh-001-k mindspeed technologies ? 292 mindspeed proprietary and confidential 4.1.6 pics proforma references 1. the atm forum, af-phy-0086.001, inverse multiplexing for atm (ima) specification version 1.1. 2. iso/iec 9646-1: 1990, information technology - open systems interconnection - conformance testing methodology and framework - part 1: general concepts (see also itu-t recommendation x.290 (1991)). 3. iso/iec 9646-2: 1990, information technology - open systems interconnection - conformance testing methodology and framework - part 2: abstract test suite specification (see also itu-t recommendation x.291 (1991)). 4. itu-t recommendation i.432 series, ?b-isdn user-network interface - physical layer specification?, april 1996. 5. itu-t recommendation i.610, ?b-isdn operation and maintenance principles and functions?, 1995. 4.2 boundary scan please contact mindspeed for information and files for boundary scan. table 4-10. ima interaction with plane management functions item protocol feature cond. for status status pred. ref. support ipm.1 does the implementation process ima group configuration indications received from the plane management? m (r-158) yes x no__ ipm.2 does the implementation process ima link addition/deletion indications received from the plane management? m (r-158) yes x no__ ipm.3 does the implementation send ima service operational status change indications to the plane management? m (r-158) yes x no__ ipm.4 does the implementation send tx/rx cell rate change indications to the plane management? m (r-158) yes x no__ comments: plane management software required to interface with driver api. table 4-11. management information base (mib) functions item protocol feature cond. for status status pred. ref. support mib.1 does the implementation support a um based on snmp? o (o-32) yes x no__ mib.2 does the implementation implement the mandatory objects in the ima-mibs defined in appendix a on page 106? (o-32) m (cr-17) yes__ no x mib.3 does the implementation implemen t the optional objects in the ima mibs defined in appendix a on page 106? (o-32) o (o-33) yes__ no x comments: support for mib objects implemented. requires snmp agent software to cr eate mib using driver api.
appendices 28529-dsh-001-k mindspeed technologies ? 293 mindspeed proprietary and confidential 4.3 power sequencing the vgg pin provides esd protection when interfacing with 5v systems. vgg must be connected to 5v for 5v i/o tolerance. when 5v tolerance is not required it is recommended that vgg be tied to the same power supply as vdd33. during power up and power down the designer should take caution as vgg should not exceed vdd33 by more than 3.6v, except for short durations identified in the note below. vgg must never be less than vdd33 by more than 0.5v. note: vgg can exceed vdd33 by up to 5v (10%) for short durations of less than 10 ms. vgg must never be less than vdd33 by more than 0.5v.
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